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AM29LV002B-120ECB Folha de dados(PDF) 8 Page - Advanced Micro Devices |
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AM29LV002B-120ECB Folha de dados(HTML) 8 Page - Advanced Micro Devices |
8 / 34 page 8 Am29LV002 PR EL I M I NAR Y Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- min g, the d evice dra ws active current u ntil th e operation is completed. In the DC Characteristics table, ICC3 and ICC4 repre- sents the standby current specifications. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en ergy co nsu mp tion . The d evice au tomat ic ally enables this mode when addresses remain stable for t AC C + 30 ns . T he automati c s l eep m ode i s independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table repre se n ts the automa ti c sl eep mo de c u r rent specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the in- ternal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RE- SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 13 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state. |
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