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AM29F800BB-70FCB Folha de dados(PDF) 10 Page - Advanced Micro Devices |
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AM29F800BB-70FCB Folha de dados(HTML) 10 Page - Advanced Micro Devices |
10 / 39 page 10 Am29F800B P R E L I M I NARY Table 3. Am29F800BB Bottom Boot Block Sector Address Table Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information. Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addi- tion, when verifying sector protection, the sector ad- dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Ad- dress Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the program- ming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Defini- tions table. This method does not require VID. See “Command Definitions” for details on using the autose- lect mode. Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) (x16) Address Range (x8) Address Range SA0 0 000 00 X 16/8 00000h–01FFFh 00000h–03FFFh SA1 0 0 0 0 0 1 0 8/4 02000h–02FFFh 04000h–05FFFh SA2 0 0 0 0 0 1 1 8/4 03000h–03FFFh 06000h–07FFFh SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh SA4 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh SA5 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh SA6 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh SA7 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh SA8 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh SA9 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh SA10 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh SA11 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh SA12 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh SA13 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh SA14 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh SA15 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh SA16 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh SA17 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh SA18 1 1 1 1 X X X 64/32 78000h–7FFFFh F0000h–FFFFFh |
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