1.

General description

The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin

compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7A.

The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and

3-state outputs. The shift registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP).

The data in each register is transferred to the storage register on a positive-going

transition of the storage register clock input (STCP). If both clocks are connected together,

the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.

It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The

storage register has 8 parallel 3-state bus driver outputs. Data in the storage register

appears at the output whenever the output enable input (OE) is LOW.

2.

Features and benefits

The 74VHC595 operates with CMOS input level

40 C to +85 C and from 40 C to +125 C

3.

Applications

74VHC595; 74VHCT595

8-bit serial-in/serial-out or parallel-out shift register with

output latches

Rev. 2 — 4 July 2012

Product data sheet