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AD120T Folha de dados(PDF) 4 Page - AMIC Technology

Nome de Peças AD120T
Descrição Electrónicos  3-Level / 258 Outputs TFT LCD Gate Driver
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Fabricante Electrônico  AMICC [AMIC Technology]
Página de início  http://www.amictechnology.com
Logo AMICC - AMIC Technology

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AD120
PRELIMINARY
(August, 2001, Version 0.0)
3
AMIC Technology, Inc
Input/Output Pin Function
Pin No.
Symbol
I/O
Description
11
CP
I
Clock pulse
7
R /L
I
Right / left direction control for shift register
When
R /L is LOW, data are shifted to the right, or ST1 / ST2
output0
output1
.…
output257.
When R /L is HIGH, data are shifted to the left, or ST1X / ST2X
output257
output256
.
...
output0.
8
XON
I
XON to force all the outputs to VH voltage.
It is not synchronous to CP.
9
XOFF
I
XOFF to force all the outputs to VOFF voltage.
It is not synchronous to CP.
6
OGW
I
Output Gate pulse Width to select output_waveform format.
4,5,
13,14
ST1, ST2,
ST1X, ST2X
I/O
When
R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined
as outputs .
The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses.
When
R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined
as outputs.
The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses.
18 - 275
OUT0~
OUT257
O
Output drivers
These outputs are synchronized to CP pulses.
The output format and voltage level are controlled by OGW, XON, XOFF , ST1 /
ST2, ST1X / ST2X and
R /L correspondingly as shown in the diagram.
12
VSS
PWR
Reference voltage
10
VDD
PWR
Supply voltage for logic operation
VDD and VSS are voltage levels of input / output logic signals
3, 15
VH
PWR
High voltage for output drivers
1, 17
VL
PWR
Low voltage for output drivers
2, 16
VOFF
PWR
OFF voltage for output drivers


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