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TDA5051AT Folha de dados(PDF) 5 Page - NXP Semiconductors |
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5 / 29 page TDA5051A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 13 January 2011 5 of 29 NXP Semiconductors TDA5051A Home automation modem 8. Functional description Both transmission and reception stages are controlled either by the master clock of the microcontroller or by the on-chip reference oscillator connected to a crystal. This ensures the accuracy of the transmission carrier and the exact trimming of the digital filter, thus making the performance totally independent of application disturbances such as component spread, temperature, supply drift and so on. The interface with the power network is made by means of an LC network (see Figure 15). The device includes a power output stage that feeds a 120 dB μV (RMS) signal on a typical 30 Ω load. To reduce power consumption, the IC is disabled by a power-down input (pin PD): in this mode, the on-chip oscillator remains active and the clock continues to be supplied at pin CLK_OUT. For low-power operation in reception mode, this pin can be dynamically controlled by the microcontroller, see Section 8.4 “Power-down mode”. When the circuit is connected to an external clock generator (see Figure 6), the clock signal must be applied at pin OSC1 (pin 7); OSC2 (pin 8) must be left open-circuit. Figure 7 shows the use of the on-chip clock circuit. All logic inputs and outputs are compatible with TTL/CMOS levels, providing an easy connection to a standard microcontroller I/O port. The digital part of the IC is fully scan-testable. Two digital inputs, SCANTEST and TEST1, are used for production test: these pins must be left open-circuit in functional mode (correct levels are internally defined by pull-up or pull-down resistors). 8.1 Transmission mode To provide strict stability with respect to environmental conditions, the carrier frequency is generated by scanning the ROM memory under the control of the microcontroller clock or the reference frequency provided by the on-chip oscillator. High frequency clocking rejects the aliasing components to such an extent that they are filtered by the coupling LC network and do not cause any significant disturbance. The data modulation is applied through pin DATA_IN and smoothly applied by specific digital circuits to the carrier (shaping). Harmonic components are limited in this process, thus avoiding unacceptable disturbance of the transmission channel (according to CISPR16 and EN50065-1 recommendations). A −55 dB Total Harmonic Distortion (THD) is reached when the typical LC coupling network (or an equivalent filter) is used. The DAC and the power stage are set in order to provide a maximum signal level of 122 dB μV (RMS) at the output. The output of the power stage (TX_OUT) must always be connected to a decoupling capacitor, because of a DC level of 0.5VDD at this pin, which is present even when the device is not transmitting. This pin must also be protected against overvoltage and negative transient signals. The DC level of TX_OUT can be used to bias a unipolar transient suppressor, as shown in the application diagram (see Figure 15). Direct connection to the mains is done through an LC network for low-cost applications. However, an HF signal transformer could be used when power-line insulation has to be performed. |
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