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TMP141AIDGKRG4 Folha de dados(PDF) 5 Page - Texas Instruments |
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TMP141AIDGKRG4 Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 24 page TMP141 SBAS347A − MARCH 2005 − REVISED JULY 2006 www.ti.com 5 1a: Master Write timing and slave detection of the data placed on the SWD bus by the master. 1b: To place a ‘0’ on the bus, the slave does not drive the bus. 1c: To place a ‘1’ on the bus, the slave holds the bus low after detecting that the master has started a data bit. 0 µs50µs 100 µs Master Write 0 Master Write 1 t INACT t INACT t Mtr1 t Mtr0 SlvDetectData1 Master Write Start t INACT t MtrS DetectStart t INACT t Mtr0 SlvDetect_st(1) t SFEdet Master starts a bit Slave detects bus activity and does nothing, leaving the bit a 0. Master Read 0 t INACT t Mtr0 SlvDetect_st(1) t SFEdet MstDetect_1 Master starts a bit Slave pulls Bus low to send back a 1 Master Read 1 NOTE: (1) Margin from tSFEdet to tMtr0 is 2.2µs. Figure 1. TMP141 Read and Write Signal Timing |
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