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ST16C654IQ64 Folha de dados(PDF) 5 Page - Exar Corporation |
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ST16C654IQ64 Folha de dados(HTML) 5 Page - Exar Corporation |
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5 / 51 page  xr ST16C654/654D REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO 5 INTA (IRQ#) 6 15 12 O (OD) When 16/68# pin is at logic 1 for Intel bus interface, this ouput becomes channel A interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An exter- nal pull-up resistor is required for proper operation. INTB INTC INTD (N.C.) 12 37 43 21 49 55 18 63 69 O When 16/68# pin is at logic 1 for Intel bus interface, these ouputs become the interrupt outputs for channels B, C, and D. The output state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, these out- puts are unused and will stay at logic zero level. Leave these out- puts unconnected. INTSEL - 65 87 I Interrupt Select (active high, input with internal pull-down). When 16/68# pin is at logic 1 for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable the interrupt outputs. Inter- rupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and disable the interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See MCR bit-3 description for full detail. This pin must be at logic 0 in the Motorola bus interface mode. Due to pin limitations on 64 pin packages, this pin is not available. To cover this limitation, two 64 pin LQFP packages ver- sions are offered. This pin is bonded to VCC internally in the ST16C654D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. TXRDYA# TXRDYB# TXRDYC# TXRDYD# - - - - - - - - 5 25 56 81 O UART channels A-D Transmitter Ready (active low). The outputs provide the TX FIFO/THR status for transmit channels A-D. See Table 5. If these outputs are unused, leave them unconnected. RXRDYA# RXRDYB# RXRDYC# RXRDYD# - - - - - - - - 100 31 50 82 O UART channels A-D Receiver Ready (active low). This output pro- vides the RX FIFO/RHR status for receive channels A-D. See Table 5. If these outputs are unused, leave them unconnected. TXRDY# - 39 45 O Transmitter Ready (active low). This output is a logically ANDed status of TXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. RXRDY# - 38 44 O Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. Pin Description NAME 64-LQFP PIN # 68-PLCC PIN# 100-QFP PIN # TYPE DESCRIPTION |
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