CDC7005

3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

SCAS685L− DECEMBER 2002 − REVISED JUNE 2009

9

POST OFFICE BOX 655303

functional description of the logic

Table 5. Reference Divider M and VCXO Divider N (See Note 4)

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

DIV BY{

DEFAULT

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

2

0

0

0

0

0

0

0

0

1

0

3

0

0

0

0

0

0

0

0

1

1

4

•

•

•

0

0

0

1

1

1

1

1

1

1

128

Yes

•

•

•

1

1

1

1

1

1

1

1

0

1

1022

1

1

1

1

1

1

1

1

1

0

1023

1

1

1

1

1

1

1

1

1

1

1024

NOTE 4: If the divider value is Q, then the code will be the binary value of (Q−1).

† The frequency applied to the Divider N must be smaller than 250 MHz. A sufficient P Divider must be selected with the MUX_SEL to maintain

this criteria.

Table 6. Reference Delay M and VCXO Delay N

MD2/ND2

MD1/ND1

MD0/ND0

DELAY†

DEFAULT

0

0

0

0 ps

Yes

0

0

1

150 ps

0

1

0

300 ps

0

1

1

450 ps

1

0

0

600 ps

1

0

1

750 ps

1

1

0

1.5 ns

1

1

1

2.75 ns

† Typical values at VCC = 3.3 V, temperature = 25°C

Table 7. PFD Pulse Width Delay

PFD2

PFD1

PFD0

ADDITIONAL PULSE WIDTH†

DEFAULT

0

0

0

0 ps

Yes

0

0

1

300 ps

0

1

0

600 ps

0

1

1

900 ps

1

0

0

1.5 ns

1

0

1

2.1 ns

1

1

0

2.7 ns

1

1

1

3.7 ns

† Typical values at VCC = 3.3 V, temperature = 25°C