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AD652JP Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças AD652JP
Descrição Electrónicos  Monolithic Synchronous Voltage-to-Frequency Converter
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD652JP Folha de dados(HTML) 11 Page - Analog Devices

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AD652
Rev. C | Page 11 of 28
NC = NO CONNECT
5
7
8
NC
VIN
+
NC
NC
6
9
10
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10k
10k
16k
4k
A. PLCC 0V TO 10V INPUT
5
7
8
NC
NC
NC
6
9
10
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10k
10k
16k
4k
B. PLCC 0V TO 8V INPUT
VIN
+
5
7
8
NC
NC
NC
6
9
10
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10k
10k
16k
4k
C. PLCC 0V TO 5V INPUT
VIN
+
5
7
8
NC
VIN
±5V
NC
6
9
10
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
10k
10k
16k
4k
D. PLCC
±5V INPUT
5V REF
20
Figure 13.
PLCC CONNECTIONS
The PLCC packaged AD652 offers additional input resistors not
found on the CERDIP-packaged device. These resistors provide
the user with additional input voltage ranges. Besides the 10 V
range available using the on-chip resistor in the CERDIP the
PLCC also offers 8 V and 5 V ranges. Figure 13A to Figure 13C
show the proper connections for these ranges with positive
input voltages. For negative input voltages, the appropriate
resistor should be tied to analog ground and the input voltage
should be applied to Pin 6, the + input of the op amp.
Bipolar input voltages can be accommodated by injecting
250 µA into Pin 5 with the use of the 5 V reference and the
input resistors. For the ±5 V or ±2.5 V range, the reference
output, Pin 20, should be tied to Pin 10. The input signal should
then be applied to Pin 8 for a ±5 V signal and to Pin 7 for a
±2.5 V signal. The input connections for a ±5 V range are
shown in Figure 13D. For a ±4 V range, the input signal should
be applied to Pin 9, and Pin 20 should be connected to Pin 8.
GAIN AND OFFSET CALIBRATION
The gain error of the AD652 is laser trimmed to within ±0.5%.
If higher accuracy is required, the internal 20 kΩ resistor must
be shunted with a 2 MΩ resistor to produce a parallel equivalent
that is 1% lower in value than the nominal 20 kΩ. Full-scale
adjustment is then accomplished using a 500 Ω series trimmer.
See Figure 14 and Figure 15. When negative input voltages are
used, this 500 Ω trimmer is tied to ground and Pin 6 is the
input pin.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ONE
SHOT
AND
"D"
FLOP
QCK
D
Q
1mA
20k
AD652
SYNCHRONOUS
VOLTAGE-TO-
FREQUENCY
CONVERTER
5V
REFERENCE
VIN
+VS
0.02
µF
2M
500
250k
20k
Figure 14. CERDIP Gain and Offset Trim
4
5
6
7
8
18
17
16
15
14
9
10
11
12
13
3
2
1
20
19
1mA
5V
REFERENCE
AD652
AND
"D"
FLOP
Q
CK
D
Q
ONE
SHOT
10k
10k
16k
4k
SYNCHRONOUS
VOLTAGE-TO-FREQUENCY
CONVERTER
VIN
500
500
2M
0.02
µF
20k
350k
±3.5mV
OFFSET
TRIM
Figure 15. PLCC Gain and Offset Trim


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