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HCPL0637 Folha de dados(PDF) 5 Page - Fairchild Semiconductor

Nome de Peças HCPL0637
Descrição Electrónicos  High Speed-10 MBit/s Logic Gate Optocouplers
Download  18 Pages
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

HCPL0637 Folha de dados(HTML) 5 Page - Fairchild Semiconductor

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©2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
HCPL06XX Rev. 1.0.9
5
Transfer Characteristics (TA = -40°C to +85°C unless otherwise specified.)
Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)
*All typical values are at VCC = 5 V, TA = 25°C
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. tPLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/µs).
10. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
Symbol
DC Characteristics
Test Conditions
Min.
Typ.*
Max.
Unit
IOH
High Level Output Current
VCC = 5.5V, VO = 5.5 V, IF = 250µA,
VE = 2.0V
(2)
100
µA
VOL
Low Level Output Voltage
VCC = 5.5V, IF = 5mA, VE = 2.0V,
IOL = 13mA
(2)
0.6
V
IFT
Input Threshold Current
VCC = 5.5V, VO = 0.6V, VE = 2.0V,
IOL = 13mA
5mA
Symbol
Characteristics
Test Conditions
Min.
Typ.*
Max.
Unit
II-O
Input-Output
Insulation Leakage Current
Relative humidity = 45%,
TA = 25°C, t = 5s,
VI-O = 3000 VDC
(11)
1.0*
µA
VISO
Withstand Insulation Test Voltage
RH < 50%, TA = 25°C,
II-O ≤ 2µA, t = 1 min.
(11)
3750
VRMS
RI-O
Resistance (Input to Output)
VI-O = 500V
(11)
1012
Ω
CI-O
Capacitance (Input to Output)
f = 1MHz(11)
0.6
pF


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