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CS5231-3 Folha de dados(PDF) 7 Page - Cherry Semiconductor Corporation |
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CS5231-3 Folha de dados(HTML) 7 Page - Cherry Semiconductor Corporation |
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7 / 11 page  ∆VOUT = (∆ILOAD) (ESR) This limitation directly affects load regulation. Capacitor ESR must be minimized if output voltage must be main- tained within tight tolerances. In such a case, it is often advisable to use a parallel network of different types of capacitors. For example, electrolytic capacitors provide high charge storage capacity in a small size, while tantalum capacitors have low ESR. The parallel combination will result in a high capacity, low ESR network. It is also impor- tant to physically locate the capacitance network close to the load, and to connect the network to the load with wide PC board traces to minimize the metal resistance. The CS5231-3 has been carefully designed to be stable for output capacitances greater than 10µF with equivalent series resistance less than 1Ω. While careful board layout is important, the user should have a stable system if these constraints are met. A graph showing the region of stability for the CS5231-3 is included in the “Typical Performance Characteristics” section of this data sheet. Input Capacitors and the VIN Thresholds A capacitor placed on the VIN pin will help to improve transient response. During a load transient, the input capacitor serves as a charge “reservoir”, providing the needed extra current until the external power supply can respond. One of the consequences of providing this current is an instantaneous voltage drop at VIN due to capacitor ESR. The magnitude of the voltage change is again the product of the current change and the capacitor ESR. It is very important to consider the maximum current step that can exist in the system. If the change in current is large enough, it is possible that the instantaneous voltage drop on VIN will exceed the VIN threshold hysteresis, and the IC will enter a mode of operation resembling an oscillation. As the part turns on, the output current IOUT will increase, reaching current limit during initial charging. Increasing IOUT results in a drop at VIN such that the shutdown threshold is reached. The part will turn off, and the load current will decrease. As IOUT decreases, VIN will rise and the part will turn on, starting the cycle all over again. This oscillatory operation is most likely at initial startup when the output capacitance is not charged, and in cases where the ramp-up of the VIN supply is slow. It may also occur during the power transition when the linear regulator turns on and the PFET turns off. a 15µs delay exists between turn-on of the regulator and the AUXDRV pin pulling the gate of the PFET high. This delay prevents “chatter” during the power transitions. During this inter- val, the linear regulator will attempt to regulate the output voltage as 3.3V. If the output voltage is significantly below 3.3V, the IC will go into current limit while trying to raise VOUT. It is a short-lived phenomenon and is mentioned here to alert the user that the condition can exist. It is typi- cally not a problem in applications. Careful choice of the PFET switch with respect to RDS(ON) will minimize the volt- age drop which the output must charge through to return to a regulated state. More information is provided in the section on choosing the PFET switch. If required, using a few capacitors in parallel to increase the bulk charge storage and reduce the ESR should give better performance than using a single input capacitor. Short, straight connections between the power supply and VIN lead along with careful layout of the PC board ground plane will reduce parasitic inductance effects. Wide VIN and VOUT traces will reduce resistive voltage drops. Choosing the PFET Switch The choice of the external PFET switch is based on two main considerations. First, the PFET should have a very low turn-on threshold. Choosing a switch transistor with VGS(ON) ≈ 1V ensures the PFET will be fully enhanced with only 3.3V of gate drive voltage. Second, the switch transis- tor should be chosen to have a low RDS(ON) to minimize the voltage drop due to current flow in the switch. The formu- la for calculating the maximum allowable on-resistance is RDS(ON)(MAX) = where VAUX(MIN) is the minimum value of the auxiliary supply voltage, VOUT(MIN) is the minimum allowable out- put voltage, IOUT(MAX) is the maximum output current and 1.5 is a “fudge factor” to account for increases in RDS(ON) due to temperature. Output Voltage Sensing It is not possible to remotely sense the output voltage of the CS5231-3 since the feedback path to the error amplifier is not externally available. It is important to minimize volt- age drops due to metal resistance of high current PC board traces. Such voltage drops can occur in both the supply traces and the return traces. The following board layout practices will help to minimize output voltage errors: • Always place the linear regulator as close to both load and output capacitors as possible. • Always use the widest possible traces to connect the lin- ear regulator to the capacitor network and to the load. • Connect the load to ground through the widest possible traces. • Connect the IC ground to the load ground trace at the point where it connects to the load. Current Limit The CS5231-3 has internal current limit protection. Output current is limited to a typical value of 850mA, even under output short circuit conditions. If the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condi- tion. The IC does not contain circuitry to report this fault. Thermal Shutdown The CS5231-3 has internal temperature monitoring circuit- ry. The output is disabled if junction temperature of the IC reaches a typical value of 180°C. Thermal hysteresis is typi- VAUX(MIN) − VOUT(MIN) 1.5 × IOUT(MAX) 7 Application Information: continued |
Nº de peça semelhante - CS5231-3 |
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Descrição semelhante - CS5231-3 |
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