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CDB4225 Folha de dados(PDF) 7 Page - Cirrus Logic |
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CDB4225 Folha de dados(HTML) 7 Page - Cirrus Logic |
7 / 30 page SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 oC; VD+, VA+ = 5V±10%;Inputs: logic 0 = DGND, logic 1 = VD+, CL = 20pF) Parameter Symbol Min Max Units I 2C® Mode (H/S = floating) Note 10 SCL Clock Frequency fscl 0 100 kHz Bus Free Time Between Transmissions tbuf 4.7 µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 µs Clock Low Time tlow 4.7 µs Clock High Time thigh 4.0 µs Setup Time for Repeated Start Condition tsust 4.7 µs SDA Hold Time from SCL Falling Note 11 thdd 0 µs SDA Setup Time to SCL Rising tsud 250 ns Rise Time of Both SDA and SCL Lines tr 1 µs Fall Time of Both SDA and SCL Lines tf 300 ns Setup Time for Stop Condition tsusp 4.7 µs Notes: 10. Use of the I 2C® bus interface requires a license from Philips. I 2C® is a registered trademark of Philips Semiconductors. 11. Data must be held for sufficient time to bridge the 300ns transition time of SCL. t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL CS4225 DS86PP8 7 |
Nº de peça semelhante - CDB4225 |
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Descrição semelhante - CDB4225 |
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