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CS43L43-KZ Folha de dados(PDF) 8 Page - Cirrus Logic |
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CS43L43-KZ Folha de dados(HTML) 8 Page - Cirrus Logic |
8 / 36 page CS43L43 8 DS479PP3 3.3.2 Control Port Mode The desired format is selected via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.11.2) . For an illustration of the required relationship between LRCK, SCLK and SDATA, see Figures 2-4. 3.4 De-Emphasis Control The device includes on-chip digital de-emphasis. Figure 5 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam- ple rate, Fs. De-emphasis is not available in double-speed mode. L RCK SC L K Le ft C h a n n e l R igh t C h ann e l SDAT A +3 + 2 +1 +5 + 4 MS B -1 -2 -3 -4 -5 +3 + 2 +1 +5 + 4 -1 -2 -3 -4 MS B LS B LS B Figure 2. I2S Data LR C K SCL K Left C h a nn el R ight C h a n n e l SD AT A +3 +2 + 1 +5 +4 MS B -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 LS B MS B LS B Figure 3. Left Justified up to 24-Bit Data LR C K SC LK Le ft C h an n e l SDAT A -6 -5 -4 -3 -2 -1 -7 +1 + 2 +3 + 4 +5 3 2 clo cks MS B R ig h t C ha nn el LSB MS B +1 + 2 +3 + 4 +5 LSB -6 -5 -4 -3 -2 -1 -7 MS B Figure 4. Right Justified Data Gain dB -10dB 0dB Frequency T2 = 15 µs T1=50 µs F1 F2 3.183 kHz 10.61 kHz Figure 5. De-Emphasis Curve |
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Descrição semelhante - CS43L43-KZ |
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