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M-8888-01T Folha de dados(PDF) 9 Page - Clare, Inc.

Nome de Peças M-8888-01T
Descrição Electrónicos  DTMF Transceiver
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Fabricante Electrônico  CLARE [Clare, Inc.]
Página de início  http://www.clare.com
Logo CLARE - Clare, Inc.

M-8888-01T Folha de dados(HTML) 9 Page - Clare, Inc.

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M-8888
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9
Rev. 1
AC Characteristics
Parameter
Symbol
Min
Typ*
Max
Units
Receive signal conditions
Valid input signal levels
-
-29
-
+1
dBm
(each tone of composite signal; Notes 1, 2, 3, 5, 6, 9)
-
27.5
-
869
mV
RMS
Positive twist accept (Notes 2, 3, 6, 9)
-
-
-
6
dB
Negative twist accept (Notes 2, 3, 6, 9)
-
-
-
6
dB
Frequency deviation accept (Notes 2, 3, 5, 9)
-
± 1.5% ± 2 Hz
-
-
Nom.
Frequency deviation reject (Notes 2, 3, 5)
-
± 3.5%
-
-
Nom.
Third tone tolerance (Notes 2, 3, 4, 5, 9, 10)
-
-
-16
-
dB
Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10)
-
-
-12
-
dB
Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11)
-
-
+22
-
dB
Call progress
Lower frequency (@ -25 dBm) accept
f
LA
-
320
-
Hz
Upper frequency (@ -25 dBm) accept
f
HA
-
510
-
Hz
Lower frequency (@ -25 dBm) reject
f
LR
-
290
-
Hz
Upper frequency (@ -25 dBm) reject
f
HR
-
540
-
Hz
Receive timing
Tone present detect time
t
DP
511
14
ms
Tone absent detect time
t
DA
0.5
4
8.5
ms
Tone duration accept (the Timing Diagrams on page 10)
t
REC
--
40
ms
Tone duration reject (the Timing Diagrams on page 10)
t
REC
20
-
-
ms
Interdigit pause accept (the Timing Diagrams on page 10)
t
ID
--
40
ms
Interdigit pause reject (the Timing Diagrams on page 10)
t
DO
20
-
-
ms
Delay St to b3
t
PStb3
-13
-
µs
Delay St to RX
O-RX3
t
PStRX
-8
-
µs
Transmit timing
Tone burst duration (DTMF mode)
t
BST
50
-
52
ms
Tone pause duration (DTMF mode)
t
PS
50
-
52
ms
Tone burst duration (extended, call progress mode)
t
BSTE
100
-
104
ms
Tone pause duration (extended, call progress mode)
t
PSE
100
-
104
ms
Tone output
High group output level (R
L = 10 KΩ)VHOUT
-6.1
-
-2.1
dBm
Low group output level (R
L = 10 KΩ)VLOUT
-8.1
-
-4.1
dBm
Pre-emphasis (R
L = 10 KΩ)dBP
02
3
dB
Output distortion (R
L = 10 kΩ, 3.4 KHz bandwidth)
THD
-
-25
-
dB
Frequency deviation (f = 3.5795 MHz)
f
D
-
± 0.7
± 1.5
%
Output load resistance
R
LT
10
-
50
k
Microprocessor interface
RD, WR low pulse width
t
CL
200
-
-
ns
RD, WR high pulse width
t
CH
180
-
-
ns
RD, WR rise and fall time
t
R, tF
--
25
ns
Address hold time
t
AH
10
-
-
ns
Address setup time
t
AS
23
-
-
ns
Data hold time (read)
t
DHR
22
-
-
ns
RD to valid data delay (200 pF load)
t
DDR
-
-
150
ns
Data setup time (write)
t
DSW
45
-
-
ns
Data hold time (write)
t
DHW
10
-
-
ns
Input capacitance, D0-D3
C
IN
-5
-
pF
Output capacitance, IRQ /CP
C/
OUT
-5
-
pF


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