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ISL6115CBZA-T Folha de dados(PDF) 2 Page - Intersil Corporation |
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ISL6115CBZA-T Folha de dados(HTML) 2 Page - Intersil Corporation |
2 / 13 page 2 FN9100.7 April 29, 2010 Simplified Block Diagram Pin Configuration ISL6115, ISL6116, ISL6117, ISL6120 (8 LD SOIC) TOP VIEW + - ISET ISEN GATE VSS VDD CTIM PGOOD PWRON CLIM WOCLIM ENABLE OC 10µA FALLING EDGE DELAY 18V + - VREF + - 1.86V 12V + - R R S QN Q ENABLE POR VDD 8V RISING EDGE PULSE + - + - UV 18V 20µA 7.5k + - + - 20µA UV DISABLE ISL61xx ISET ISEN GATE VSS 1 2 3 4 8 7 6 5 PWRON PGOOD CTIM VDD Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6115CB (Note 1) ISL61 15CB 0 to +85 8 Ld SOIC M8.15 ISL6115CBZA (Notes 1, 2) 6115 CBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6116CBZA (Notes 1, 2) 6116 CBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6117CBZA (Notes 1, 2) 6117 CBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6120CBZA (Notes 1, 2) 6120 CBZ 0 to +85 8 Ld SOIC (Pb-free) M8.15 ISL6115EVAL1Z Evaluation Platform NOTES: 1. Please refer to TB347 for details on reel specifications. Add “-T” suffix for tape and reel. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6115. For more information on MSL please see techbrief TB363. ISL6115, ISL6116, ISL6117, ISL6120 |
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Descrição semelhante - ISL6115CBZA-T |
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