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AD7655-EP Folha de dados(PDF) 6 Page - Analog Devices |
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AD7655-EP Folha de dados(HTML) 6 Page - Analog Devices |
6 / 12 page AD7655-EP Rev. A | Page 6 of 12 Parameter Symbol Min Typ Max Unit SLAVE SERIAL INTERFACE MODES External SCLK Setup Time t 38 5 ns External SCLK Active Edge to SDOUT Delay t 39 3 18 ns SDIN Setup Time t 40 5 ns SDIN Hold Time t 41 5 ns External SCLK Period t 42 25 ns External SCLK High t 43 10 ns External SCLK Low t 44 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise CL is 60 pF maximum. 2 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t 25 3 17 17 17 ns Internal SCLK Period Minimum t 26 25 50 100 200 ns Internal SCLK Period Typical t 26 40 70 140 280 ns Internal SCLK High Minimum t 27 12 22 50 100 ns Internal SCLK Low Minimum t 28 7 21 49 99 ns SDOUT Valid Setup Time Minimum t 29 4 18 18 18 ns SDOUT Valid Hold Time Minimum t 30 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t 31 1 3 30 80 ns Busy High Width Maximum (Normal) t 35 3.25 4.25 6.25 10.75 µs Busy High Width Maximum (Impulse) t 35 3.5 4.5 6.5 11 µs |
Nº de peça semelhante - AD7655-EP |
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Descrição semelhante - AD7655-EP |
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