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8236-BRF-001-A M01-0590

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of their respective owners. Although Mindspeed Technologies strives for accuracy in all

its publications, this material may contain errors or omissions and is subject to change

without notice. This material is provided as is and without any express or implied

warranties, including merchantability, fitness for a particular purpose and non-

infringement. Mindspeed Technologies shall not be liable for any special, indirect, inci-

dental or consequential damages as a result of its use.

Service-Specific Performance

Accelerators

• LECID filtering and echo suppression

• Dual leaky bucket based on CLP

(frame relay)

• Frame relay DE interworking

• Internal SNMP MIB counters

• IP over ATM; supports both CLP0+1

and ABR shaping

Flexible Architectures

• Multi-peer host

• Direct switch attachment via reverse

UTOPIA

• ATM terminal

– Host control

– Local bus control

• Optional local processor New

Features

• 3.3 V, 388 BGA lowers power and

eases PCB assembly (0.75 W max)

• AAL3/4 CPCS generation and

checking

• PCI 2.1, including support for serial

EEPROM

• Enhancements to xBR Traffic

Manager

– Fewer ABR templates

– Improved CBR tunneling

• Reduced memory size for VCC

lookup tables

• Increased addressing flexibility

• Additional byte lane swappers for

increased system flexibility

• UTOPIA Level 2, 8/16 bit 50 MHz

• Programmable size routing tags for

up to 64 byte cells

• Selectable single/separate

UTOPIA clocks

• Interworking function for all

AAL1/2 scheduling

– Cell-on-demand scheduling

• Updated PM-OAM processing

per i.610

• SECBC calculated per GR-1248

• Paging function in order to gluelessly

control RS8228 cell delineator

• Robust EEPROM operation (SAR

provides power)

• Compact PCI Hot Swap capabilities

• Master PCI write over read

arbitration control

• Increase incoming DMA FIFO buffer

from 2 KB to 8 KB

• Prepended VCC index on RSM

BOM cells

• Optional reference clock drive

scheduler

• Head of line blocking protection for

multi-PHY operation

xBR Traffic Management

• TM4.1 Service Classes

– CBR

– VBR (single, dual and CLP-based

leaky buckets)

– Real-time VBR

– ABR (explicit rate, relative rate

and EFCI marking)

– UBR

– GFC (controlled and uncontrolled

flows)

– Guaranteed Frame Rate (GFR)

(guaranteed MCR on UBR VCCs)

• 16 levels of priorities (16 + CBR)

• Dynamic per-VCC scheduling

• Multiple programmable ABR

templates (supplied by Mindspeed

or user)

• Scheduler driven by selectable clock

– Local system clock

– External reference clock

• Internal RM OAM cell feedback path

• Virtual FIFO buffer rate matching

(Source Rate Matching)

• Per-VCC MCR and ICR

• Tunneling

– VP tunnels (VCI interleaving on

PDU boundaries)

– CBR tunnels (cells interleaved as

UBR, VBR or ABR with an aggregate

CBR limit)

• 155 Mbps full-duplex (2-cell PDUs)

Multi-Queue Segmentation

Processing

• 32 transmit queues with optional

priority levels

• 64 K VCCs maximum

• AAL5 and AAL3/4 CPCS generation

• AAL0 Null CPCS (optional use of PTI

for PDU demarcation)

• ATM cell header generation

• Raw cell mode (52 octet)

• 200 Mbps half-duplex

• 155 Mbps full-duplex (with 2-cell

PDUs)

• Variable length transmit FIFO buffer

– CDV-host latency matching

(1 to 9 cells)

• Symmetric Tx and Rx architecture

– Buffer descriptors

– Queues

• User defined field circulates back to

the host (32 bits)

• Distributed host or SAR-shared

memory segmentation

• Simultaneous segmentation and

reassembly

• Per-PDU control of CLP/PTI (UBR)

• Per-PDU control of AAL5 UU field

• Message and streaming status modes

• Virtual Tx FIFO buffer (PCI host)

Multi-Queue Reassembly

Processing

• 32 reassembly queues

• 64K VCCs maximum*

• AAL5 and AAL3/4 CPCS checking

• AAL0

– PTI termination

– Cell count termination

• Early Packet Discard, based on:

– Receive buffer underflow

– Receive status overflow

– CLP with priority threshold

– AAL5 max PDU length

– Rx FIFO buffer full

– Frame relay DE with priority

threshold

– LECID filtering and echo

suppression

– Per-VCC firewalls

• Dynamic channel lookup (NNI or UNI

addressing)

– Supports full address space

– Deterministic

– Flexible VCI count per VPI

– Optimized for signaling address

assignment

• Message and streaming status

modes

• Raw cell mode (52 octet)

• 200 Mbps half duplex

• 155 Mbps full duplex (with

2-cell PDUs)

• Distributed host or SAR-shared

memory reassembly

• 8 Programmable reassembly hard-

ware time outs (per-VCC assignable)

• Global max PDU length for AAL5

• Per-VCC buffer firewall (memory

usage limit)

• Simultaneous reassembly and

segmentation

• Idle cell filtering

High-Performance Host

Architecture with Buffer

Isolation

• Write-only control and status

• Read multiple command for data

transfer

• Up to 32 host clients control and

status queues

• Physical or logical clients

– Enables peer-to-peer architecture

• Descriptor-based buffer chaining

• Scatter/gather DMA

• Endian neutral (allows data word and

control word byte swapping, for both

big and little endian systems)

• Non-word (byte) aligned host buffer

addresses

• Automatically detects presence of Tx

data or Rx free buffers

• Virtual FIFO buffers (PCI bursts

treated as a single address)

• Hardware indication of BOM

• Allows isolation of system resources

• Status queue interrupt delay

Designer Toolkit

• Evaluation hardware

• Reference schematics

• Generous Implementation of OAM-

PM Protocols

• Detection of all F4/F5 OAM flows

• Internal PM monitoring and

generation for up to 128 VCCs

• Optional global OAM Rx/Tx queues

• In-line OAM insertion and generation

Standards-Based I/O

• 33 MHz PCI 2.1 (to 40 MHz)

• Serial EEPROM to store PCI

configuration information

• PHY interfaces

– UTOPIA master (Level 1)

– UTOPIA slave (Level 1)

– UTOPIA master (Level 2)

– UTOPIA slave (Level 2)

• Flexible SAR-shared memory

architecture

• Optional local control interface

• Boundary scan for board-

level testing

• Source loopback, for diagnostics

• Glueless connection to Mindspeed’s

ATM physical layer device, the

CX28250 and CN8223

Standards Compliance

• UNI/NNI 3.1

• TM 4.0 / TM 4.1 compliant

• Bellcore GR-1248

• ATM Forum B-ICI V2.0

Ordering Information

Model number: CN8236EBGB

Manufacturing part number:

28236-12P

Product revision: B

Package: 388-pin BGA

Operating temperature: -40°C to 85ºC

Product Features