1

2

3

4

9

10

11

12

8

DAP

5

7

6

VOUT

SW2

PGND

SW1

EN

FB

VSEL

MODE/

SYNC

SGND

NC*

VDD

DAP

11

12

10

9

8

7

6

5

4

3

2

1

FB

VSEL

MODE/

SYNC

SGND

NC*

VDD

VOUT

SW2

PGND

SW1

EN

LM3668

www.ti.com

SNVS449L – JUNE 2007 – REVISED MARCH 2011

Connection Diagrams

Figure 4. Top View

Figure 5. Bottom View

See Package Number DQB (WSON)

Pin Descriptions

Pin #

Pin Name

Description

1

VOUT

Connect to output capacitor.

2

SW2

Switching Node connection to the internal PFET switch (P2) and NFET synchronous rectifier (N2).

3

PGND

Power Ground.

4

SW1

Switching Node connection to the internal PFET switch (P1) and NFET synchronous rectifier (N1).

5

Supply to the power switch, connect to the input capacitor.

6

EN

Enable Input. Set this digital input high for normal operation. For shutdown, set low.

7

VDD

Signal Supply input. If board layout is not optimum an optional 1µF ceramic capacitor is suggested as

close to this pin as possible.

8

NC

No connect. Connect this pin to SGND on PCB layout.

9

SGND

Analog and Control Ground.

10

MODE/SYNC

Mode = LOW, Automatic Mode. Mode= HI, Forced PWM Mode SYNC = external clock synchronization

from 1.6MHz to 2.7MHz (When SYNC function is used, device is forced in PWM mode).

11

VSEL

Voltage selection pin; ( ie: 2.8V/3.3V option) Logic input low (or GND) = 2.8V and logic high = 3.3V (or

12

FB

Feedback Analog Input. Connect to the output at the output filter.

DAP

DAP

Die Attach Pad, connect the DAP to SGND on PCB layout to enhance thermal performance. It should

not be used as a primary ground connection.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2007–2011, Texas Instruments Incorporated

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