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TSB41AB3-EP Folha de dados(PDF) 1 Page - Texas Instruments |
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TSB41AB3-EP Folha de dados(HTML) 1 Page - Texas Instruments |
1 / 56 page TSB41AB3EP IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER SGLS122C − JULY 2002 − REVISED JUNE 2008 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −40 °C to 85°C and −55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product Change Notification D Qualification Pedigree† D Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus‡ and the 1394a-2000 Supplement D Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394 D Fully Compliant With Open HCI Requirements D Provides Three 1394a-2000 Fully-Compliant Cable Ports at 100/200/400 Megabits Per Second (Mbits/s) D Full 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume D Extended Resume Signaling for Compatibility With Legacy DV Devices D Ultralow Power Sleep Mode D Node Power Class Information Signaling for System Power Management D Cable Power Presence Monitoring † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D Cable Ports Monitor Line Conditions for Active Connection to Remote Node D Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down D Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz D Interface to Link Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation D Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies D Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies D Low Cost 24.576-MHz Crystal Provides Transmit Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz D Separate Cable Bias (TPBIAS) for Each Port D Single 3.3-V Supply Operation D Low-Cost High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package D Direct Drop-In Upgrade for TSB41LV03APFP and TSB41LV03PFP D Software Device Reset (SWR) D Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41AB3 Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane D The TSB41AB3 Has a 1394a Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise Copyright 2008, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. PowerPAD is a trademark of Texas Instruments. ‡Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation FireWire is a trademark of Apple Computer, Incorporated. |
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