TSB41AB3

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

9

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

NO.

I/O

DESCRIPTION

SM

CMOS

33

I

Test control input. This input is used in the manufacturing test of the TSB41AB3. For normal use

this terminal is tied to GND.

SYSCLK

CMOS

2

O

System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to

the LLC.

TESTM

CMOS

31

I

Test control input. This input is used in the manufacturing test of the TSB41AB3. For normal use

this terminal is tied to VDD through a 1-kΩ resistor.

TPA0+

TPA1+

TPA2+

Cable

45

52

58

I/O

Twisted-pair cable A differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

TPA0−

TPA1−

TPA2−

Cable

44

51

57

I/O

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. For an unused port, TPA+ and TPA− can be left

open.

TPB0+

TPB1+

TPB2+

Cable

43

50

56

I/O

Twisted-pair cable B differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals should be kept matched and as short as possible to the

external load resistors and to the cable connector. For each unused port, TPB+ and TPB−

TPB0−

TPB1−

TPB2−

Cable

42

49

55

I/O

external load resistors and to the cable connector. For each unused port, TPB+ and TPB−

terminals can be tied together and then connected to ground through a 1-k

Ω resistor or the TPB+

and TPB− terminals can be connected to the suggested termination network.

TPBIAS0

TPBIAS1

TPBIAS2

Cable

46

53

59

I/O

Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper

operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that

there is an active cable connection. Each of these terminals, except for an unused port, must be

decoupled with a 1.0-

µF capacitor to ground. For the unused port, this terminal can be left

unconnected.

VDD-5V

Supply

9

−

5-V VDD terminal. This terminal must be connected to the LLC VDD supply when a 5-V LLC is

used, and connected to the PHY DVDD when a 3-V LLC is used. A combination of high-frequency

decoupling capacitors near this terminal is suggested, such as paralleled 0.1

µF and 0.001 µF.

When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless of the

state of the ISO terminal. When this terminal is tied to a 3-V supply, bus holders are enabled when

the ISO terminal is high.

XI

XO

Crystal

76

77

−

Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental

mode crystal. The optimum values for the external shunt capacitors are dependent on the

specifications of the crystal used (see crystal selection in the Applications Information section).

When an external clock source is used, XI should be the input and XO should be left open, and the

clock must be supplied before the device is taken out of reset.

NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures.

Signals tied to ground may be tied directly.