SCLK

CS

CS

FOUR ZEROS

DB6

DONTC DONTC

ADD2

ADD1

ADD0

DONTC DONTC DONTC

DB7

DB5

DB4

B1

12

8

7

6

5

4

3

2

1

DB0

DIN

DOUT

SCLK

CS

13

14

FOUR ZEROS

15

16

8

9

10

11

12

13

14

15

16

Track

Hold

Power Up

ADD2 ADD1 ADD0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DIN

DOUT

SCLK

CS

Control register

1

2

3

4

5

6

7

1

2

3

4

5

6

7

ADD2 ADD1 ADD0

8

DB7

DB6

DB5

Power

Down

Power Up

Track

Hold

ADC088S052

SNAS340F – SEPTEMBER 2005 – REVISED MARCH 2013

www.ti.com

ADC088S052 Timing Specifications (continued)

Symbol

Parameter

Conditions

Typical

Units

DOUT falling

2.4

20

ns (max)

CS Rising Edge to DOUT High-

Impedance

DOUT rising

0.9

20

ns (max)

Timing Diagrams

Figure 1. ADC088S052 Operational Timing Diagram

Figure 2. ADC088S052 Serial Timing Diagram

Figure 3. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold

capacitor is charged by the input voltage.

6

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