1-531

Notes:

1. Not to exceed 5% duty factor, not to exceed 50

µsec pulse width.

2. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads

or terminals shorted together.

3. This is a momentary withstand test, not an operating condition.

4. t

edge of the output pulse. The t

the 1.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |t

5. CM

(V

logic high state (V

6. Duration of output short circuit time not to exceed 10 ms.

7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the V

still remain in the desired logic state. For desired logic high state, V

8. Measured between adjacent input pairs shorted together for each multichannel device.

9. Each channel.

10. Standard parts receive 100% testing at 25

°C (Subgroups 1 and 9). SMD and hi-rel parts receive 100% testing at 25, 125, and –55°C

(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).

11. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to

limits specified for all lots not specifically tested.

12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of

optocouplers with the same part number that are all switching at the same time under the same operating conditions.

13. The HCPL-6430 and HCPL-6431 dual channel parts function as two independent single channel units. Use the single channel

parameter limits.

Figure 1. Typical Logic Low Output

Voltage vs. Logic Low Output Current.

Figure 2. Typical Logic High Output

Voltage vs. Logic High Output Current.

Figure 3. Typical Output Voltage vs.

Input Forward Current.

Figure 4. Typical Diode Input Forward

Current Characteristic.