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AD7013 Folha de dados(PDF) 8 Page - Analog Devices |
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AD7013 Folha de dados(HTML) 8 Page - Analog Devices |
8 / 20 page –8– REV. A AD7013 Limit at T A = Parameter –40 °C to +85°C Units Description t 26 Power up Receive to RxCLK 10240t 1 ns max CR13 = 0; Rx Offset Autocalibration On 6144t 1 ns max CR13 = 1; Rx Offset autocalibration Off t 27 30 ns min Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge 85 ns max t 28 4t 1 ns RxCLK Cycle Time; CR10 = 0; 2x Sampling of the Symbol Rate t 29 2t 1–20 ns min RxCLK High Pulse Width; CR10 = 0 t 30 2t 1–20 ns min RxCLK Low Pulse Width; CR10 = 0 t 31 –10 ns min RxCLK Rising Edge to RxFRAME Rising Edge +10 ns max RxCLK to RxFRAME Propagation Delay t 32 64t 1 ns RxFRAME Cycle Time; CR10 = 0 t 33 4t 1 ns RxFRAME High Pulse Width; CR10 = 0 t 34 –10 ns min Propagation Delay from RxCLK Rising Edge to RxDATA Valid +10 ns max t 35 12t 1 ns min DxCLK Rising Edge to Last Falling Edge of RxCLK 128t 1 ns max t 36 2t 1 + 20 ns max 3-State to Receive Channel Valid t 37 2t 1 + 20 ns max Receive Channel to 3-State Relinquish Time (V AA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz; T A = TMIN to TMAX, unless otherwise noted) RECEIVE SECTION TIMING 1t 37 is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance. MCLK (I) RxCLK (O) RxFRAME (O) RxDATA (O) t 27 t 29 t 30 t 31 t 32 t 34 t 26 1MSB DxCLK (O) CR14 NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT 0 The last DxCLK edge which is used to write to Command Reg One, setting CR14 to One The last DxCLK edge which is used to write to Command Reg One, setting CR14 to Zero t 35 t 28 Q LSB 1LSB Q MSB 15-BIT I WORD 1 I/Q FLAG BIT 15-BIT I WORD I/Q FLAG BIT t 33 Figure 4. Receive Serial Interface Timing with 2 × Sampling of the Symbol Rate (CR10 = 0) RxCLK (O) RxFRAME (O) RxDATA (O) t36 DxCLK (O) CR18 NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT The last DxCLK edge which is used to write to Command Reg One, setting CR14 to Zero t37 The last DxCLK edge which is used to write to Command Reg One, setting CR14 to One 3- STATE ACTIVE 3- STATE Figure 5. Receive Serial Interface 3-State Timing OBSOLETE |
Nº de peça semelhante - AD7013_15 |
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Descrição semelhante - AD7013_15 |
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