ADV478/ADV471

–5–

REV. B

PIN FUNCTION DESCRIPTION

Pin

Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level as

illustrated in Tables IV and V. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the

pixel and overlay inputs are ignored

SETUP

pedestal.

SYNC

Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source

on the analog outputs (see Figures 3 and 4). SYNC does not override any other control or data input, as shown in

Tables IV and V; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge

of CLOCK.

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the P0–P7, OL0–OL3, SYNC, and BLANK

inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedi-

cated TTL buffer.

P0–P7

Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the

color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. P0

is the LSB. Unused inputs should be connected to GND.

OL0–OL3

Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color informa-

tion, as illustrated in Table III. When accessing the overlay palette, the P0–P7 inputs are ignored. They are

latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND.

IOR, IOG, IOB

Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a

doubly terminated 75

Ω coaxial cable (Figures 5 and 6).

Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the

full-scale output current.

current on each output is:

Ω) = K × 1,000 × V

current on each output is:

Mode

Pedestal

K

6-Bit

7.5 IRE

3.170

147

8-Bit

7.5 IRE

3.195

147

6-Bit

0 IRE

3.000

147

8-Bit

0 IRE

3.025

147

COMP

Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If an

µF ceramic capacitor must always be

Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a 1.2 V

(typical) reference. If an external current reference is used (Figure 6), this pin should be left floating, except for

the bypass capacitor. A 0.1

µF ceramic capacitor must always be used to decouple this input to V

Figures 5 and 6.

OPA

Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to

COMP. When using an external current reference (Figure 6), this pin should be left floating.

GND

Analog ground. All GND pins must be connected to the Ground Plane.

WR

Write control input (TTL compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are

latched on the falling edge of WR during MPU write operations. See Figure 1.

OBSOLETE