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ILC7281 Folha de dados(PDF) 8 Page - Impala Linear Corporation |
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ILC7281 Folha de dados(HTML) 8 Page - Impala Linear Corporation |
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8 / 9 page  Micropower Dual 150mA CMOS RF-LDO™ Regulators with Power Supply Reset Monitor Impala Linear Corporation 8 (408) 574-3939 www.impalalinear.com Nov 2000 ILC7281 1.0 Advance 6 5 4 3 1 2 INPUT VOLTAGE (V IN) DETECT RELEASE VOLTAGE (V DR) DETECT FAIL VOLTAGE (V DF) MINIMUM OPERATING VOLTAGE (V MIN) GROUND VOLTAGE (V SS) OUTPUT VOLTAGE (V OUT) GROUND VOLTAGE (V SS) The following designators 1~6 refer to the timing diagram below. 1. While the input voltage (VIN) is higher than the detect fail voltage (VDF); the VOUT output pin is at high impedence state. 2. When the input VIN voltage falls lower than VDF, VOUT drops near to ground voltage. 3. If the input voltage decreases below the minimum oper- ating voltage (VMIN), the VOUT output becomes unstable. In this condition, if the VOUT pin is pulled up, VOUT indicates the VIN voltage. 4. During an increase of the input voltage from VSS voltage, VOUT is not stable in the voltage below the VMIN. Exceeding that level, the output stays at the ground level (VSS) between the minimum operating voltage (VMIN) and detect release voltage (VDR). 5. If the input voltage increases more than VDR, the VOUT output pin is at high impedence state. 6. The difference between VDR and VDF is the hysteresis in the system. Functional Descriptin - Power Supply Reset Monitor Timing Diagram |
Nº de peça semelhante - ILC7281 |
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Descrição semelhante - ILC7281 |
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