5

LOW to HIGH input transition voltage. As long as the slope of

the RES input voltage remains in the same direction (increas-

ing or decreasing) around the RES input transition voltage, the

RESET output will make a single transition.

Ready Operation

The 82C284 accepts two ready sources for the system ready

signal which terminates the current bus cycle. Either a synchro-

nous (SRDY) or asynchronous ready (ARDY) source may be

used. Each ready input has an enable (SRDYEN and

ARDYEN) for selecting the type of ready source required to ter-

minate the current bus cycle. An address decoder would nor-

mally select one of the enable inputs.

READY is enabled (LOW), if either SRDY + SRDYEN = 0 or

ARDY + ARDYEN = 0 when sampled by the 82C284 READY

generation logic. READY will remain active for at least two CLK

cycles.

The READY output has an open-drain driver allowing other

ready circuits to be wired with it, as shown in Figure 4. The

READY signal of an 80C286 system requires an external

pull-up resistor. To force the READY signal inactive (HIGH)

at the start of a bus cycle, the READY output floats when

either S1 or S0 are sampled LOW at the falling edge of CLK.

Two system clock periods are allowed for the pull-up resistor

READY is forced active one CLK later (see Waveforms).

Figure 5 illustrates the operation of SRDY and SRDYEN.

These inputs are sampled on the falling edge of CLK when

S1 and S0 are inactive and PCLK is HIGH. READY is forced

active when both SRDY and SRDYEN are sampled as LOW.

Figure 6 shows the operation of ARDY and ARDYEN These

inputs are sampled by an internal synchronizer at each fall-

ing edge of CLK. The output of the synchronizer is then sam-

pled when PCLK is HIGH. If the synchronizer resolved both

the ARDY and ARDYEN as active, the SRDY and SRDYEN

inputs are ignored. Either ARDY or ARDYEN must be HIGH

when using the ARDY and ARDYEN inputs as a basis for

generating READY.

READY remains active until either S1 or S0 are sampled

LOW, or the ready inputs are sampled as inactive.

1N914

10k

Ω

FIGURE 3. TYPICAL RC RES TIMING CIRCUIT

10

µF

11

82C284

RES

+

47

Ω

C1

7

8

X1

X2

F/C

82C284

CLK

READY

CLK

80C286

CPU OR

SUPPORT

COMPONENT

READY

6

10

4

18

DECOUPLING

CAPACITOR

FIGURE 4. RECOMMENDED CRYSTAL AND READY

CONDITIONS

82C284