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AD7849ARZ-REEL Folha de dados(PDF) 7 Page - Analog Devices |
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AD7849ARZ-REEL Folha de dados(HTML) 7 Page - Analog Devices |
7 / 20 page AD7849 Rev. C | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREF+ VDD NC VOUT ROFS VREF– VSS SYNC RSTIN RSTOUT AGND SCLK VCC SDOUT DCEN BIN/COMP DGND LDAC SDIN CLR 1 2 3 4 20 19 18 17 5 16 6 15 7 14 8 13 9 12 10 11 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. AD7849 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VREF+ VREF+ Input. The DAC is specified for VREF+ of 5 V. The DAC is fully multiplying so that the VREF+ range is +5 V to –5 V. 2 VREF− VREF− Input. The DAC is specified for VREF− of –5 V. The DAC is fully multiplying so that the VREF− range is –5 V to +5 V. 3 VSS Negative supply for the analog circuitry. This is nominally –15 V. 4 SYNC Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data-word. 5 SCLK Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge. 6 VCC Positive supply for the digital circuitry. This is nominally 5 V. 7 SDOUT Serial Data Output. With DCEN at Logic 1, this output is enabled, and the serial data in the input shift register is clocked out on each rising edge of SCLK. 8 DCEN Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used; otherwise, this pin must be connected low. 9 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In the unipolar output range, natural binary format is selected by connecting the input to Logic 0. In the bipolar output range, offset binary is selected by connecting this input to Logic 0, and twos complement is selected by connecting it to a Logic 1. 10 DGND Digital Ground. Ground reference point for the on-chip digital circuitry. 11 LDAC Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this signal, or alternatively, if this input is permanently low, an automatic update mode is selected where the DAC is updated on the 16th falling SCLK edge. 12 SDIN Serial Data Input. The 16-bit serial data-word is applied to this input. 13 CLR Clear Logic Input. Taking this input low sets VOUT to 0 V in both the unipolar output range and the bipolar twos complement output range. It sets VOUT to VREF– in the offset binary bipolar output range. 14 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying Logic 0 to this input, resets the DAC output to 0 V. In normal operation, it should be tied to Logic 1. 15 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It can be used to control other system components, if desired. 16 AGND This is the analog ground for the device. It is the point to which the output gets shorted in reset mode. 17 VDD Positive Supply for the Analog Circuitry. This is 15 V nominal. 18 NC No Connect. Leave unconnected. 19 VOUT DAC Output Voltage Pin. 20 ROFS Input to Summing Resistor of DAC Output Amplifier. This is used to select the output voltage ranges. Also, see Figure 20 to Figure 23 in the Applying the AD7849 section. |
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