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AD7896 Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças AD7896
Descrição Electrónicos  2.7 V to 5.5 V, 12-Bit, 8s ADC in 8-Lead SOIC/PDIP
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD7896 Folha de dados(HTML) 11 Page - Analog Devices

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AD7896
–11–
Figure 9 shows a histogram plot for 8192 conversions of a dc
input using the AD7896 with a 3.3 V supply. The analog input
was set at the center of a code transition. It can be seen that
almost all the codes appear in the one output bin, indicating
very good noise performance from the ADC. The rms noise
performance for the AD7896 for the plot below was 111
µV.
9000
0
2000
1000
3000
4000
5000
6000
7000
8000
1005
1006
CODE
f SAMPLE = 95kHz,
f SCLK = 8.33MHz,
AIN CENTERED ON CODE 1005
RMS NOISE = 0.138 LSB
Figure 9. Histogram of 8192 Conversions of a DC Input
The same data is presented in Figure 10 as in Figure 9, except
that in this case, the output data read for the device occurs
during conversion. This has the effect of injecting noise onto the
die while bit decisions are being made and this increases the
noise generated by the AD7896. The histogram plot for 8192
conversions of the same dc input now shows a larger spread of
codes with the rms noise for the AD7896 increasing to 279
µV.
This effect will vary depending on where the serial clock
edges appear with respect to the bit trials of the conversion
process. It is possible to achieve the same level of performance
when reading during conversion as when reading after conver-
sion, depending on the relationship of the serial clock edges to
the bit trial points.
8000
0
2000
1000
1004
4000
3000
5000
6000
7000
1005
1006
CODE
f SAMPLE = 95kHz,
f SCLK = 8.33MHz,
AIN CENTERED ON
CODE 1005, RMS
NOISE = 0.346 LSB
Figure 10. Histogram of 8192 Conversions with
Read during Conversion
SDATA
BUSY
SCLK1
DR1
AD7896
SCLK
IRQ2
RFS1
Figure 7.
AD7896–DSP56002/L002 Interface
Figure 8 shows an interface circuit between the AD7896 and the
DSP56002/L002 DSP processor. The DSP56002/L002 is con-
figured for normal mode asynchronous operation with gated
clock. It is also set up for a 16-bit word with SCK as gated clock
output. In this mode, the DSP56002/L002 provides 16 serial
clock pulses to the AD7896 in a serial read operation. The
DSP56002/L002 assumes valid data on the first falling edge of
SCK so the interface is simply 2-wire as shown in Figure 8.
The BUSY line from the AD7896 is connected to the MODA/
IRQA input of the DSP56002/L002 so that an interrupt will be
generated at the end of conversion. This ensures that the read
operation will take place after conversion is finished.
SDATA
BUSY
SCK
SDR
DSP56002/L002
AD7896
SCLK
MODA/
IRQA
Figure 8. AD7896 to DSP56002/L002 Interface
AD7896 PERFORMANCE
Linearity
The linearity of the AD7896 is determined by the on-chip 12-bit
DAC. This is a segmented DAC that is laser trimmed for 12-bit
integral linearity and differential linearity. Typical relative accu-
racy numbers for the part are
±1/4 LSB, while the typical DNL
errors are
±1/2 LSB.
Noise
In an ADC, noise exhibits itself as code uncertainty in dc appli-
cations and as the noise floor (in an FFT, for example) in ac
applications. In a sampling ADC like the AD7896, all informa-
tion about the analog input appears in the baseband from dc
to 1/2 the sampling frequency. The input bandwidth of the
track-and-hold exceeds the Nyquist bandwidth and, therefore,
an antialiasing filter should be used to remove unwanted
signals above fS/2 in the input signal in applications where
such signals exist.
Rev. D
AD7896 to ADSP-2105 Interface
ADSP-2105
An alternative scheme is to configure the ADSP-2105 such
that it accepts an external noncontinuous serial clock. In this
case, an external noncontinuous serial clock is provided that
drives the serial clock inputs of both the ADSP-2105 and the
AD7896. In this scheme, the serial clock frequency is limited
to 10 MHz by the AD7896.


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