High Performance 12-Bit, 6-Channel Output,

AD8382

PRODUCT FEATURES

High accuracy, high resolution voltage outputs

12-bit input resolution

Laser trimmed outputs

Fast settling, high voltage drive

33 ns settling time to 0.25% into 200 pF load

Slew rate 390 V/

µs

Outputs to within 1.3 V of supply

High update rates

Fast, 120 Ms/s data update rate

Voltage controlled video reference (brightness) and

full-scale (contrast) output levels

Flexible logic

STSQ/XFR allow parallel AD8382 operation

INV bit reverses polarity of video signal

Output overload protection

Low static power dissipation: 743 mW

Includes STBY function

3.3 V logic, 9 V to 18 V analog supplies

Available in 48-lead 7 mm × 7 mm LFCSP

APPLICATIONS

LCD analog column driver

PRODUCT DESCRIPTION

The AD8382 DecDriver provides a fast, 12-bit latched decimat-

ing digital input that drives six high voltage outputs.12-bit input

words are sequentially loaded into six separate, high speed,

bipolar DACs. A flexible digital input format allows several

AD8382s to be used in parallel for higher resolution displays.

STSQ synchronizes sequential input loading, XFR controls

synchronous output updating, and R/L controls the direction of

loading as either left-to-right or right-to-left. Six channels of

high voltage output drivers drive to within 1.3 V of the rail. The

output signal can be adjusted for dc reference, signal inversion,

and contrast for maximum flexibility.

The AD8382 is fabricated on Analog Devices’ XFHV, fast

bipolar 26 V process, providing fast input logic bipolar DACs

with trimmed accuracy and fast settling, high voltage, precision

drive amplifiers on the same chip. The AD8382 dissipates

743 mW nominal static power. The STBY pin reduces power to

a minimum, with fast recovery.

FUNCTIONAL BLOCK DIAGRAM

VREFHI

VREFLO

VID2

VID3

VID4

VID5

VID1

VID0

AD8382

STBY

BYP

R/L

E/O

CLK

STSQ

XFR

INV

V1

V2

DB(0:11)

2-STAGE

2-STAGE

2-STAGE

2-STAGE

2-STAGE

2-STAGE

LATCH

LATCH

LATCH

LATCH

LATCH

LATCH

12

12

12

12

12

12

12

12

12

12

12

12

SCALING

CONTROL

SEQUENCE

CONTROL

BIAS

12

12

DAC

DAC

DAC

DAC

DAC

DAC

Figure 1. Functional Block Diagram

Rev. 0

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Specifications subject to change without notice. No license is granted by implication

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