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AD9040A Folha de dados(PDF) 8 Page - Analog Devices |
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AD9040A Folha de dados(HTML) 8 Page - Analog Devices |
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8 / 16 page  REV. D –8– AD9040A FREQUENCY (MHz) 2.5 5.0 0 0 –65 ENCODE = 40.5MSPS f1 IN = 2.25MHz @ –7dBFS f2 IN = 2.35MHz @ –7dBFS 2f1 – f2 = –69.4dBFS 2f2 – f1 = –69.2dBFS TPC 10. FFT Response FREQUENCY (MHz) 10.0 20.2 0 0 –65 ENCODE = 40.5MSPS ANALOG IN = 2.3MHz SNR = 55.20dB SNR (w/o har.) = 55.90dB SECOND HARMONIC = –75.1dB THIRD HARMONIC = –73.2dB TPC 11. FFT Response FREQUENCY (MHz) 10.0 20.2 0 0 –65 ENCODE = 40.5MSPS ANALOG IN = 10.3MHz SNR = 53.38dB SNR (w/o har.) = 54.31dB SECOND HARMONIC = –64.7dB THIRD HARMONIC = –73.7dB TPC 12. FFT Response THEORY OF OPERATION The AD9040A employs subranging architecture and digital error correction. This combination of design techniques ensures true 10-bit accuracy at the digital outputs of the converter. At the input, the analog signal is applied to a track-and-hold (T/H) that holds the analog value that is present when the unit is strobed with an encode command. The conversion process begins on the rising edge of this pulse, which should have a 50% ( ± 10%) duty cycle. The minimum encode rate of the AD9040A is 10 MSPS because of the use of three inter- nal track-and-hold devices. The held analog value of the first track-and-hold is applied to a 5-bit flash converter and a pair of internal track-and-hold devices (shown in the Functional Block Diagram as a single unit). The track-and-hold devices pipeline the analog signal to the ampli- fier array through a residue ladder and switching circuit while the 5-bit flash converter resolves the most significant bits (MSB) of the held analog voltage. When the 5-bit flash converter has completed its cycle, its out- put activates 1 of 32 ladder switches; these in turn cause the correct residue signal to be applied to the error amplifier array. The output of the error amplifier is applied to a 6-bit flash con- verter whose output supplies the five least significant bits (LSB) of the digital output along with one bit of error correction for the 5-bit main range converter. Decode logic aligns the data from the two converters and pre- sents the result as a 10-bit parallel digital word. The output stage of the AD9040A is CMOS. Output data are strobed on the trailing edge of the encode command. The full-scale range of the AD9040A is determined by the refer- ence voltage applied to the VREF (Pin 6) input. This voltage sets the internal flash and residue ladder voltage drops; these estab- lish the value of the LSB. Because of headroom restraints, the full-scale range cannot be increased by applying a higher than specified reference voltage. Conversely, a lower reference volt- age will reduce the full-scale range of the converter but will also decrease its performance. An internal band gap reference volt- age of 2.5 V is provided to assure optimum performance over the operating temperature range. USING THE AD9040A Timing The duty cycle of the encode clock for the AD9040A is critical for obtaining the rated performance of the ADC. Internal pulsewidths within the track-and-hold are established by the encode command pulsewidth; to ensure rated performance, the duty cycle should be held at 50%. Duty cycle variations of less than ±10% will cause no degradation in performance. Operation at encode rates less than 10 MSPS is not recom- mended. The internal track-and-hold saturates, causing erroneous conversions. This track-and-hold saturation precludes clocking the AD9040A in burst mode. The 50% duty cycle must be maintained even for sample rates down to 10 MSPS. The AD9040A provides latched data outputs, with 2 1/2 pipe- line delays. Data outputs are available one propagation delay (tPD) after the falling edge of the encode command (see Figure 1). The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9040A; these transients can detract from the converter’s dynamic per- formance. Voltage Reference A stable voltage reference is required to establish the 2 V p-p range of the AD9040A. There are two options for creating this reference. The easiest and least expensive way to implement it is to use the (2.5 V) band gap voltage reference which is internal to the ADC. Figure 3 illustrates the connections for using the internal reference. The internal reference has 500 µA of extra drive current that can be used for other circuits. REF AMP BAND GAP REFERENCE REFERENCE 2.5V AD9040A 0.1 F VOUT VREF –VS BPREF Figure 3. Using Internal Reference |
Nº de peça semelhante - AD9040A_15 |
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Descrição semelhante - AD9040A_15 |
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