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AD9042 Folha de dados(PDF) 3 Page - Analog Devices |
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AD9042 Folha de dados(HTML) 3 Page - Analog Devices |
3 / 24 page AD9042 Rev. B | Page 3 of 24 SPECIFICATIONS DC SPECIFICATIONS AVCC = DVCC = 5 V; VREF tied to VOFFSET through 50 Ω; TMIN = −40°C, TMAX = +85°C. Table 1. Parameter1 Temperature Test Level Min Typ Max Unit RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI −10 ±3 +10 mV Offset Tempco Full V 25 ppm/°C Gain Error Full VI −6.5 0 +6.5 % FS Gain Tempco Full V −50 ppm/°C REFERENCE OUT (VREF)2 25°C V 2.4 V ANALOG INPUT (AIN) Input Voltage Range VREF ± 0.500 V Input Resistance Full IV 200 250 300 Ω Input Capacitance 25°C V 5.5 pF ENCODE INPUT3 Logic Compatibility4 TTL/CMOS Logic 1 Voltage Full VI 2.0 5.0 V Logic 0 Voltage Full VI 0 0.8 V Logic 1 Current (VINH = 5 V) Full VI 450 625 800 μA Logic 0 Current (VINL = 0 V) Full VI −400 −300 −200 μA Input Capacitance 25°C V 2 pF DIGITAL OUTPUTS Logic Compatibility CMOS Logic 1 Voltage (IOH = 10 μA) 25°C I 3.5 4.2 V Full IV 3.5 V Logic 0 Voltage (IOL = 10 μA) 25°C I 0.75 0.80 V Full IV 0.85 V Output Coding Twos complement POWER SUPPLY AVCC Supply Voltage Full VI 5.0 V AVCC Current (I) Full V 109 mA DVCC Supply Voltage Full VI 5.0 V DVCC Current (I) Full V 10 mA ICC (Total) Supply Current Full VI 119 147 mA Power Dissipation Full VI 595 735 mW Power Supply Rejection Ratio (PSRR) 25°C I −20 ±1 +20 mV/V Full V ±5 mV/V 1 C1 (Pin 10) tied to GND through a 0.01 μF capacitor. 2 VREF is normally tied to VOFFSET through 50 Ω. If VREF is used to provide dc offset to other circuits, it should first be buffered. 3 ENCODE driven by single-ended source; ENCODE bypassed to ground through a 0.01 μF capacitor. 4 ENCODE may also be driven differentially in conjunction with ENCODE; see the Encoding the AD9042 section for details. |
Nº de peça semelhante - AD9042_15 |
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Descrição semelhante - AD9042_15 |
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