Data Sheet

AD9259

Rev. E | Page 7 of 52

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

Parameter1, 2

Temp

Min

Typ

Max

Unit

CLOCK3

Maximum Clock Rate

Full

50

MSPS

Minimum Clock Rate

Full

10

MSPS

Full

10

ns

Full

10

ns

OUTPUT PARAMETERS3

Full

2.0

2.7

3.5

ns

Full

300

ps

Full

300

ps

Full

2.0

2.7

3.5

ns

Full

ns

Full

ps

Full

ps

Data to Data Skew

Full

±50

±150

ps

Wake-Up Time (Standby)

25°C

600

ns

Wake-Up Time (Power-Down)

25°C

375

μs

Pipeline Latency

Full

8

CLK

cycles

APERTURE

25°C

500

ps

Aperture Uncertainty (Jitter)

25°C

<1

ps rms

Out-of-Range Recovery Time

25°C

2

CLK

cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were

completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI.

4