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Os motores de busca de Datasheet de Componentes eletrônicos |
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AD9380 Folha de dados(PDF) 11 Page - Analog Devices |
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AD9380 Folha de dados(HTML) 11 Page - Analog Devices |
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11 / 60 page  AD9380 Rev. 0 | Page 11 of 60 Mnemonic Description POWER SUPPLY1 VD (3.3 V) Analog Power Supply. These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible. VDD (1.8 V to 3.3 V) Digital Output Power Supply. A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise). These supply pins are identified separately from the VD pins, so output noise transferred into the sensitive analog circuitry can be minimized. If the AD9380 is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 1.8 V) for compatibility. PVDD (1.8 V) Clock Generator Power Supply. The most sensitive portion of the AD9380 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. DVDD (1.8 V) Digital Input Power Supply. This supplies power to the digital logic. GND Ground. The ground return for all circuitry on chip. It is recommended that the AD9380 be assembled on a single solid ground plane, with careful attention to ground current paths. 1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD. |
Nº de peça semelhante - AD9380_15 |
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Descrição semelhante - AD9380_15 |
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