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ADM1070 Folha de dados(PDF) 4 Page - Analog Devices |
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ADM1070 Folha de dados(HTML) 4 Page - Analog Devices |
4 / 16 page REV. 0 –4– ADM1070 PIN CONFIGURATION TOP VIEW (Not to Scale) 6 5 4 SENSE VIN GATE UV/OV TIMER ADM1070ART 1 2 3 VEE PIN FUNCTION DESCRIPTION Pin No. Mnemonic Function 1 SENSE Connection to External FET Source Voltage. A sense resistor is connected in the supply path between the SENSE Pin and VEE, and the voltage across this resistor is monitored to detect current faults. This voltage is fed as an input to the linear current regulator. When it reaches 100 mV for a specified period, tON, the regulator reduces the gate voltage and drives the FET as a linear pass device. If current monitoring is not required, this feature can be turned off by shorting the SENSE Pin and VEE together. 2VEE Device Negative Supply Voltage. This pin should be connected to the lower potential of the power supply. 3VIN Shunt Regulated On-Chip Supply, Nominally VEE + 12.3 V. This pin should be current fed through a dropper resistor that is connected to the higher potential of the power supply inputs. 4TIMER Allows User Control over Timing Functions by Determining Frequency of Oscillator. Fre- quency set by connecting external capacitor to VEE. Tying pin directly to VEE causes oscillator to default to internally set value. 5 UV/OV Input Pin for Overvoltage and Undervoltage Detection Circuitry. The voltage appearing on the UV/OV Pin is proportional to board supply and is determined by external resistors. When the voltage on UV/OV falls below the undervoltage threshold of 0.86 V, the GATE Pin is driven low. When the voltage appearing at the UV/OV Pin rises above the overvoltage threshold of 1.97 V, the GATE Pin is also driven low. If the external resistor ratio of R1/R2 = 40 is used, then this gives an operating range of –36 V to –77 V. 6 GATE Output to External FET Gate Drive. Controlled by linear current regulator. The gate is driven low if an overvoltage or undervoltage fault occurs or if a current fault lasts for longer than the time, tON. When in linear regulation, the GATE Pin voltage is controlled as part of the servo loop. No external compensation is required. When the FET is fully enhanced and the load capacitance has been charged, the GATE Pin reaches a high level of typically 12 V. |
Nº de peça semelhante - ADM1070_15 |
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Descrição semelhante - ADM1070_15 |
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