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ISL5239KI Folha de dados(PDF) 8 Page - Intersil Corporation |
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ISL5239KI Folha de dados(HTML) 8 Page - Intersil Corporation |
8 / 31 page 8 pre-distorter. The pre-distorter block diagram is shown in Figure 4. Serial Interface The serial interface for the external memory effects calculation consists of outputs SERCLK, SERSYNC, and SEROUT and input SERIN. The serial output sends the 32- bit unsigned average power off-chip for further processing. The data is transmitted via the SEROUT pin MSB first, with the first bit marked by a high pulse on the SERSYNC pin. The SERCLK rate is scaled such that 32 bits are transmitted in one period of the power integrator as controlled by register 0x18 bits 5:4. SEROUT is enabled by register 0x18 bit 12. The SERIN receives the thermal compensation parameters from external processing using the same SERCLK and SERSYNC used by the SEROUT. The chip expects to receive 32 bits of data sequentially on the SERIN pin: the MSB of A, followed by the rest of A, then the MSB of B, followed by the rest of B. The SERIN is enabled by register 0x18 bit 8. When SERIN is disabled, registers 0x19 and 0x1a supply the A and B parameters for the thermal compensation calculations. See Figure 16 for a detailed timing diagram of the serial interface. IF Converter (IFC) The output of the pre-distorter is a complex baseband signal sampled at the system CLK rate. To provide greater system flexibility, the IF Converter function can change this in one of three different ways, providing frequency shifts, sample rate changes and complex to real conversions. Real 1X The real 1x operating mode shifts the signal up by Fs/4 and performs a complex to real conversion without changing the base sample rate. This mode has 1/2 the bandwidth of the original input signal, with the I output channel active and the Q output channel set to 0. The operation of the IF converter in this mode is shown in Figure 5. Real 2X The real 2x operating mode converts complex to real at 2x the sample rate and shifts the signal up to Fs/2 (Fs/4 of the output rate). This mode has the same bandwidth as the original signal with the I channel carrying the first of twwo samples/clock and the Q channel carrying the second sample. The operation of the IF Converter in this mode is shown in Figure 6. FIGURE 4. PRE-DISTORTER BLOCK DIAGRAM Q I BYPASS FROM IFIP Q I CM TEST Q I MEMORY FUNC. SEL. OFFSET SCALE POWER LUT PWR INTGR PER. PAR. TO SERIAL SER. OUTPUT EN. EFFECTS FPGA LUT DATA I LUT DATA Q LUT DELTA DATA I EXTERNAL ADDR LUT DELTA DATA Q ACTIVE LUT LUT ADDR LUT ADDR AUTO INCR. POWER PWR LOW PWR HIGH PD MAG. INTEGRATOR SERCLK SERSYNC SEROUT SERIAL TO PAR. SERIAL INPUT EN. COEF. A COEF. B MEMORY EFFECT COMPENSATION DATA LUT ADDRESS CALCULATION COEF. B SELECT TEST FIGURE 5. IF CONVERTER IN REAL 1X MODE OPERATION Q I FROM PD HALF ej(pi/2)(n) BAND FILTER Re{*} I BYPASS FIGURE 6. IF CONVERTER IN REAL 2X MODE OPERATION Q I FROM PD HALF ej(pi/2)(n) BAND FILTER Re{*} 2 Z-1 2 2 2 Q I BYPASS ISL5239 |
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