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ISL57404IN Folha de dados(PDF) 6 Page - Intersil Corporation

Nome de Peças ISL57404IN
Descrição Electrónicos  3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL57404IN Folha de dados(HTML) 6 Page - Intersil Corporation

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3-6
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (I/QIN+ - I/QIN-)
-
±0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
Analog Input Resistance, RIN+ or RIN-
VIN+, VIN- = VREF, DC
-
1
-
M
Analog Input Capacitance, CIN+ or CIN-
VIN+, VIN- = VREF, DC
-
10
-
pF
Analog Input Bias Current, IB+ or IB-VIN+, VIN- = VREF, DC
(Notes 2, 3)
-10
-
10
µA
Differential Analog Input Bias Current
IBDIFF = (IB+- IB-)
(Notes 2, 3)
-0.5
-
0.5
µA
Full Power Input Bandwidth, FPBW
(Note 2)
-
400
-
MHz
Analog Input Common Mode Voltage Range
(VIN++ VIN-) / 2
Differential Mode (Note 2)
0.25
-
AVCC-0.25
V
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT (Loaded)
-
1.25
-
V
Reference Output Current, IROUT
-1
-
mA
Reference Temperature Coefficient
-
200
-
ppm/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
-
1.25
-
V
Total Reference Resistance, RRIN
With VRIN = 1.25V
-
-
-
M
Reference Current, IRIN
With VRIN = 1.25V
-
-
-
mA
SAMPLING CLOCK INPUT
Input Logic High Voltage, VIH
CLK
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK
-
-
0.8
V
Input Logic High Current, IIH
CLK, VIH = 5V
-1
-
1
µA
Input Logic Low Current, IIL
CLK, VIL = 0V
-1
-
1
µA
Input Capacitance, CIN
CLK
-
-
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100µA
2.45
2.98
-
V
Output Logic Low Voltage, VOL
IOL = 100µA
-
0.001
0.5
V
Output Capacitance, COUT
-7
-
pF
TIMING CHARACTERISTICS
Aperture Delay, tAP
--
-
ns
Aperture Delay Match
-
100
-
ps
Aperture Jitter, tAJ
-5
-
psRMS
Data Output Hold, tH
-3
-
ns
Data Output Delay, tOD
-
4.5
-
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
-
7
-
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
-
Cycles
Sample Clock Pulse Width (Low)
(Note 2)
7.5
8.3
-
ns
Electrical Specifications
AVCC = DVCC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25
oC; Differential Analog Input, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL5740


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