LF3310 datasheet(10/21 Pages) LODEV

Nome de Peças	LF3310

Descrição Electrónicos	Horizontal / Vertical Digital Image Filter

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Fabricante Electrônico	LODEV [LOGIC Devices Incorporated]

Página de início	http://www.logicdevices.com

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DEVICES INCORPORATED

LF3310

Horizontal / Vertical Digital Image Filter

10

Video Imaging Products

11/08/2001-LDS.3310-H

changed every clock cycle. This is

useful when filtering interleaved

data. When loading limit values into

the device, the upper limit must be

greater than the lower limit. Limit

register loading is discussed in the LF

InterfaceTM section.

Vertical Filter

The vertical filter is designed to filter

a digital image in the vertical dimen-

sion. It is a FIR filter which can be

configured to have as many as 8-taps.

Line Buffers

There are seven on-chip line buffers.

The maximum delay length of each

line buffer is 3076 cycles and the

minimum is 4 cycles. Configuration

Register 2 (CR2) determines the delay

length of the line buffers. The line

buffer length is equal to the value of

CR2 plus 4. A value of 0 for CR2 sets

the line buffer length to 4. A value of

3072 for CR2 sets the line buffer

length to 3076. Any values for CR2

greater than 3072 are not valid.

The line buffers have two modes of

operation: delay mode and recirculate

mode. Bit 0 of Configuration Register

3 determines which mode the line

buffers are in. In delay mode, the

data input to the line buffer is delayed

by an amount determined by CR2. In

recirculate mode, the output of the

line buffer is routed back to the input

of the line buffer allowing the line

buffer contents to be read multiple

times.

Bit 1 of Configuration Register 3

allows the line buffers to be loaded in

parallel. When Bit 1 is “1”, the input

register (DIN11-0) loads all seven line

buffers in parallel. This allows all the

line buffers to be preloaded with data

in the amount of time it normally

takes to load a single line buffer.

VSHEN enables or disables the

loading of data into the line buffers

when the device is in Dimensionally

Separate Mode (see the VSHEN

section for a full discussion). When in

Orthogonal Mode, VSHEN also

enables or disables the loading of data

into the input register (DIN11-0) and

the forward and reverse I/D Registers.

It is important to note that in Or-

thogonal Mode, either HSHEN or

VSHEN can disable the loading of

data into the input register (DIN11-0),

I/D Registers, and line buffers. Both

must be active to enable data loading

in Orthogonal Mode.

Interleaved Data

The vertical filter is capable of

handling interleaved data. The

number of data sets it can handle is

determined by the number of data

values contained in a video line. If

the interleaved video line has 3076

data values or less, the vertical filter

can handle it no matter how many

data sets are interleaved together.

BITS

FUNCTION

DESCRIPTION

11-0

Line Buffer Length

See Line Buffer Description Section

TABLE 4.

CONFIGURATION REGISTER 2 – ADDRESS 202H

BITS

FUNCTION

DESCRIPTION

0

Line Buffer Mode

0 : Delay Mode

1 : Recirculate Mode

1

Line Buffer Load

0 : Normal Load

1 : Parallel Load

11-2

Reserved

Must be set to “0”

TABLE 5.

CONFIGURATION REGISTER 3 – ADDRESS 203H

BITS

FUNCTION

DESCRIPTION

0

HV Filter Mode

0 : Orthogonal Mode

1 : Dimensionally Separate

1

HV Direction

0 : Horizontal to Vertical

1 : Vertical to Horizontal

3-2

Orthogonal Kernel Size

00 : 3-3 Kernel

01 : 5-5 Kernel

10 : 7-7 Kernel

11 : Not Used

4

Limit Register Load Control

0 : Limit Registers Always Enabled

1 : Limit Registers Under Shift Enable Control

11-5

Reserved

Must be set to “0”

TABLE 6.

CONFIGURATION REGISTER 4 – ADDRESS 204H

BITS

FUNCTION

DESCRIPTION

0

Vertical Limit Enable

0 : Vertical Limiting Disabled

1 : Vertical Limiting Enabled

1

Horizontal Limit Enable

0 : Horizontal Limiting Disabled

1 : Horizontal Limiting Enabled

11-2

Reserved

Must be set to “0”

TABLE 7.

CONFIGURATION REGISTER 5 – ADDRESS 205H

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