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LF48212 Folha de dados(PDF) 2 Page - LOGIC Devices Incorporated |
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LF48212 Folha de dados(HTML) 2 Page - LOGIC Devices Incorporated |
2 / 9 page DEVICES INCORPORATED LF48212 12 x 12-bit Alpha Mixer 2 Video Imaging Products 08/16/2000–LDS.48212-F SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers except for the Delay Control Register. Inputs DINA11-0 — Pixel Data Input A DINA11-0 is one of the 12-bit regis- tered data input ports. Data is latched on the rising edge of CLK. DINB11-0 — Pixel Data Input B DINB11-0 is the other 12-bit registered data input port. Data is latched on the rising edge of CLK. α11-0 — Alpha Mix Input α11-0 determines the weighting applied to the data input signals before being mixed together. DINA11-0 and DINB11-0 receive weightings of α and 1.0 – α respectively. α11-0 is unsigned and restricted to the range of 0 to 1.0. Figure 1 shows the data format for α11-0. If a value greater than 1.0 is latched into the Alpha Mix Input, internal circuitry will force the value to be equal to 1.0. Data is latched on the rising edge of CLK. DEL — Delay Data Input DEL is used to load the Delay Control Register. The Delay Control Register contains a 15-bit value which deter- mines the number of delay stages added to the input and control signals. The 15-bit data value is loaded serially into the Delay Control Register using DEL and LD. Data present on DEL is latched on the rising edge of LD. FIGURE 1. ALPHA MIX INPUT FORMAT 11 10 9 6 5 4 87 3210 2 0 2 –1 2–2 2 –5 2–6 2–7 2 –3 2–4 2 –8 2–9 2–10 2–11 Outputs DOUT12-0 — Data Output DOUT12-0 is the 13-bit registered data output port. Controls TC — Data Format Control TC determines if the input data is in unsigned or two’s complement format. If TC is LOW, the data is in two’s complement format. If TC is HIGH, the data is in unsigned format. Data present on TC is latched on the rising edge of CLK. TC only affects the data that is being latched into the LF48212. Changing TC does not affect internal data already in the pipeline. MIXEN — Alpha Mix Input Enable When HIGH, data on α11-0 is latched into the LF48212 on the rising edge of CLK. When LOW, data on α11-0 is not latched and the last value loaded is held as the alpha mix value. LD — Load Strobe The rising edge of LD latches the data on DEL into the Delay Control Register. BYPASS — Bypass Delay Stage Control The BYPASS control is used to bypass the internal programmable delay stages. When BYPASS is set HIGH, the Delay Control Register will automatically be loaded with a “0”. This will set the number of program- mable delay stages to zero for all input and control signals. When BYPASS is LOW, the desired number of delay stages can be set by loading RND1-0 ROUNDING FORMAT 00 Round to 8-bits 01 Round to 10-bits 10 Round to 12-bits 11 Round to 13-bits TABLE 1. OUTPUT ROUNDING the Delay Control Register with the appropriate value. Note that this signal is not intended to change during active operation of the LF48212. RND1-0 — Output Rounding Control RND1-0 determines how the output of the LF48212 is rounded. The output may be rounded to 8, 10, 12, or 13-bits. Table 1 lists the different rounding possibilities and the associated value for RND1-0. Rounding is accom- plished by adding a “1” to the bit to the right of what will become the least significant bit. Then the bit that had the “1” added to it and all bits to the right of it are set to “0”. Data present on RND1-0 is latched on the rising edge of CLK. When RND1-0 is latched in, it only applies to the video input data latched in at the same time. Changing RND1-0 does not affect the rounding format for internal data already in the pipeline. OE — Output Enable When OE is LOW, DOUT12-0 is enabled for output. When OE is HIGH, DOUT12-0 is placed in a high- impedance state. |
Nº de peça semelhante - LF48212 |
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Descrição semelhante - LF48212 |
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