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STC5415 Folha de dados(PDF) 6 Page - Connor-Winfield Corporation |
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STC5415 Folha de dados(HTML) 6 Page - Connor-Winfield Corporation |
6 / 48 page Page 6 of 48 TM120 Rev:P1.3 Date: September 20, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5415 Line Card Clock Data sheet Preliminary STC5415 Pin Description All I/O is LVCMOS, except for CLK1 is LVPECL/LVDS. REF4 and REF5 are LVCMOS/LVPECL/LVDS. Table 1: Pin Description Pin Name Pin # I/O Description AVCC 4,14 3.3V analog power input AGND 3,15 Analog ground VCC 8, 9, 12, 22, 32, 36, 38, 39, 45, 46, 54, 57 3.3V digital power input GND 1, 7, 10, 11, 21, 31, 40, 53, 58 Digital ground RST 48 I Active low to reset the chip MCLK 6 I Master clock input (TCXO or XO) EVENT_INTR 5 O Event interrupt EX_SYNC 28 I Frame Sync signal REF1 29 I Reference input 1 REF2 30 I Reference input 2 REF3 34 I Reference input 3 REF4_P 23 I Differential reference input 4 (LVPECL/LVDS) REF4_N 24 I Differential reference input 4 (LVPECL/LVDS) REF5_P 25 I Differential reference input 5 (LVPECL/LVDS) REF5_N 26 I Differential reference input 5 (LVPECL/LVDS) CLK1_P 19 O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1 LVPECL or LVDS CLK1_N 20 O Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1 LVPECL or LVDS CLK2 56 O Clock output CLK2, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G4. LVCMOS. CLK8K 17 O 8kHz frame pulse signal, from Synthesizer F, 50% duty cycle or programmable pulse width CLK2K 18 O 2kHz frame pulse signal, from Synthesizer F, 50% duty cycle or programmable pulse width SRCSW 13 I Hard-wired manual reference pre-selection CS 44 I SPI bus chip select SCLK 47 I SPI bus clk SDI 43 I SPI bus data in SDO 52 O SPI bus data out CLKE 42 I SPI Clock edge selection |
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