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STC5423 Folha de dados(PDF) 10 Page - Connor-Winfield Corporation |
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STC5423 Folha de dados(HTML) 10 Page - Connor-Winfield Corporation |
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10 / 60 page  Page 10 of 60 TM114 Rev:1.4 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5423 Synchronous Clock for SETS Data sheet Note 1: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for the sharing registers 0x20~0x3F. 0x2D Short_Term_Accu_History 31-0 R Short term Accumulated History 0x2E 0x2F 0x30 0x31 User_Specified_History 31-0 R/W User programmed holdover history 0x32 0x33 0x34 0x35 History_Ramp 7-0 R/W Controls long term history and short term history accumulation bandwidth and the locking stage’s frequency ramp control 0x36 Ref_Priority_Table 7-0 R/W REF1-2 selection priority 0x3C PLL_Status 7-6, 4-0 R PLL status. SYNC, LOS, LOL, OOP, SAP, DHT, HHA 0x3D Holdover_Accu_Flush 0 W Flush/reset the long-term history and the device holdover history 0x3E PLL_Event_Out 7-0 R/W PLL event out (Reserved) 0x3F PLL_Event_In 7-0 R/W PLL event in: Relock 0x4A Synth_Index_Select 3-0 R/W Determines which synthesizer is selected for setting frequency value and adjusting phase skew 0x4B Synth_Freq_Value 17-0 R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer index is selected at the reg- ister Synth_Index_Select 0x4C 0x4D 0x4E Synth_Skew_Adj 11-0 R/W Adjusts phase skew for the synthesizer, based on which synthesizer index is selected at the register Synth_Index_Select 0x4F 0x50 CLK1/2_Signal_Level 1-0 R/W Selects the signal level (LVPECL or LVDS) for clock outputs CLK1 and CLK2 0x51 CLK1_Sel 1-0 R/W Selects synthesizer G1 or enable tri-state for CLK1 0x52 CLK2_Sel 1-0 R/W Selects synthesizer G2 or enable tri-state for CLK2 0x53 CLK3_Sel 1-0 R/W Selects synthesizer (G3 or GT4) or enable tri-state for CLK3 0x54 CLK4_Sel 1-0 R/W Selects synthesizer (G4 or GT4) or enable tri-state for CLK4 0x55 CLK5_Sel 1-0 R/W Selects synthesizer (G5 or GT4) or enable tri-state for CLK5 0x56 CLK6_Sel 1-0 R/W Selects synthesizer (G6 or GT4) or enable tri-state for CLK6 0x57 CLK7_Sel 1-0 R/W Selects synthesizer (G7 or GT4) or enable tri-state for CLK7 0x59 CLK8K_Sel 6-0 R/W 8kHz frame pulse clock output duty cycle and frame edge selection 0x5A CLK2K_Sel 6-0 R/W 2kHz frame pulse clock output duty cycle and frame edge selection 0x70 Field_Upgrade_Status 2-0 R Indicates the status of field upgrade process 0x71 Field_Upgrade_Data 7-0 R/W Loads 7600 bytes of firmware configuration data 0x72 Field_Upgrade_Count 12-0 R Counts byte numbers that have been loaded 0x73 0x74 Field_Upgrade_Start 7-0 W Writes three values consecutively to start the field upgrade process 0x7F MCLK_Freq_Reset 7-0 R/W Select the frequency of the external oscillator Table 2: Register Map Addr Reg Name Bits Type Description |
Nº de peça semelhante - STC5423 |
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Descrição semelhante - STC5423 |
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