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TS3DDR32611 Folha de dados(PDF) 2 Page - Texas Instruments

Nome de Peças TS3DDR32611
Descrição Electrónicos  1A Peak Sink/Source PCDDR3 Termination Regulator with Integrated Isolation Switch and Low Power Mode Operation
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

TS3DDR32611 Folha de dados(HTML) 2 Page - Texas Instruments

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C
B
A
1
2
3
VTT
VTT
GND
VLDO
IN
CH23
CH21
VDDQ
VDD
CH22
VTT
EN
CH24
CH20
PGND
VTT
REF
VTT
SNS
NC
GND
ODT
EN
CH25
CH19
GND
GND
GND
CH15
CH11
CH7
CH17
CH13
CH9
CH16
CH12
CH8
GND
GND
GND
GND
GND
GND
CH18
CH14
CH10
CH1
CH3
CH5
CH4
CH2
CH0
CH6
F
E
D
G
4
5
6
7
Switch I/O
GND
LDO Power
LDO I/O
Control
C
B
A
7
6
5
VTT
VTT
GND
VLDO
IN
CH23
CH21
VDDQ
VDD
CH22
VTT
EN
CH24
CH20
PGND
VTT
REF
VTT
SNS
NC
GND
ODT
EN
CH25
CH19
GND
GND
GND
CH15
CH11
CH7
CH17
CH13
CH9
CH16
CH12
CH8
GND
GND
GND
GND
GND
GND
CH18
CH14
CH10
CH1
CH3
CH5
CH4
CH2
CH0
CH6
F
E
D
G
4
3
2
1
NC
TS3DDR32611
SCDS347A – AUGUST 2013 – REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DIE SIZE: 4.0 mm × 4.0 mm
BUMP PITCH: 0.5 mm
TS3DDR32611 Pin Mapping(1)
7
6
5
4
3
2
1
G
CH5
CH9
CH13
CH17
CH22
VDD
VDDQ
F
CH3
CH7
CH11
CH15
CH21
CH23
VLODIN
E
CH1
GND
GND
GND
GND
VTT
VTT
D
CH0
GND
GND
GND
GND
NC
VTTSNS
C
CH2
GND
GND
GND
VREF
PGND
B
CH4
CH8
CH12
CH16
CH20
CH24
VTT_EN
A
CH6
CH10
CH14
CH18
CH19
CH25
ODT_EN
(1)
The NC must be floating, and cannot be connected to anything.
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NO.
NAME
C4, C5, C6, D3, D4, D5,
GND
Signal Ground
D6, E3, E4, E5, E6
E1, E2
VTT
O
Power output for VTT LDO, need to connect 10-
μF or greater MLCC for stability
C1
PGND
Power GND for VTT LDO
D1
VTTSNS
I
VTT LDO voltage sense input
F1
VLDOIN
I
Power supply input for VTT/ VTTREF
C2
VREF
O
VREF buffered reference output. Need to connect 0.22-
μF or greater MLCC for stability.
B1
VTT_EN
I
Enable signal for VTT and VREF output
A1
ODT_EN
I
Enable signal for Switch
G1
VDDQ
I
VDDQ input, reference input for VREF
G2
VDD
I
Device power supply input 3.3 V typical
D7, E7, C7, F7, B7, G7,
A7, F6, B6, G6, A6, F5,
B5, G5, A5, F4, B4, G4,
CH0-CH25
I/O
Switch input or output
A4, A3, B3, F3, G3, F2,
B2, A2
D2
NC
Not connected, must be floating and cannot be connected to any signal
2
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Copyright © 2013, Texas Instruments Incorporated
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