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ISL29011IROZ-T7 Folha de dados(PDF) 9 Page - Intersil Corporation

Nome de Peças ISL29011IROZ-T7
Descrição Electrónicos  Digital Ambient Light Sensor and Proximity Sensor with Interrupt Function
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29011IROZ-T7 Folha de dados(HTML) 9 Page - Intersil Corporation

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ISL29011
9
FN6467.6
May 1, 2014
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I2C Interface
There are eight 8-bit registers available inside the ISL29011. The
two command registers define the operation of the device. The
command registers do not change until the registers are
overwritten. The two 8-bit data Read Only registers are for the ADC
output and the Timer output. The data registers contain the ADC's
latest digital output. The four 8-bit interrupt registers hold 16-bit
interrupt high and low thresholds.
The ISL29011’s I2C interface slave address is internally hard-wired
as 1000100. When 1000100x with x as R or W is sent after the
Start condition, this device compares the first seven bits of this byte
to its address and matches.
Figure 3 shows a sample one-byte read. Figure 4 shows a sample
one-byte write. The I2C bus master always drives the SCL (clock) line,
while either the master or the slave can drive the SDA (data) line.
Figure 4 shows a sample write. Every I2C transaction begins with the
master asserting a start condition (SDA falling while SCL remains
high). The following byte is driven by the master, and includes the
slave address and read/write bit. The receiving device is responsible
for pulling SDA low during the acknowledgement period. Every I2C
transaction ends with the master asserting a stop condition (SDA
rising while SCL remains high).
For more information about the I2C standard, please consult the
PhilipsI2C specification documents.
FIGURE 3. I2C READ TIMING DIAGRAM SAMPLE
START
W A
A
A6 A5 A4 A3 A2 A1 A0 W
A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W A
A
A
A D7D6 D5 D4 D3 D2D1 D0
13
5
7
13
57
1 2 3
4 5
6
9
2
4
6
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29011
DATA BYTE0
REGISTER ADDRESS
OUT
DEVICE ADDRESS
I2C DATA
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
24
68 9
2
46
8 9
7
8
13
5
7
8
9
I2C SDA
I2C SDA
I2C CLK
IN
FIGURE 4. I2C WRITE TIMING DIAGRAM SAMPLE
START
W
A
A
A6 A5 A4 A3 A2 A1 A0 W
A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0
A
A
1
2
615
948
STOP
SDA DRIVEN BY MASTER
FUNCTIONS
REGISTER ADDRESS
DEVICE ADDRESS
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
I2C DATA
I2C SDA IN
I2C SDA OUT
I2C CLK IN
AA
34
5
7
8
9
2
3
4
6
7
8
1
2
3
5
67
9
A


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