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ISL29033IROZ-EVALZ Folha de dados(PDF) 5 Page - Intersil Corporation |
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ISL29033IROZ-EVALZ Folha de dados(HTML) 5 Page - Intersil Corporation |
5 / 15 page ISL29033 5 FN7656.2 February 25, 2013 VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V ISDA SDA Current Sinking Capability VOL = 0.4V 4 5 mA IINT INT Current Sinking Capability VOL = 0.4V 4 5 mA NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. A 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count as a fluorescent light with illuminance at the stated lux. 8. An 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count as solar light with illuminance at the stated lux. I2C Electrical Specifications For SCL and SDA (Figure 2), unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% and 1MΩ 1% tolerance. PARAMETER DESCRIPTION CONDITION MIN (Note 6) TYP MAX (Note 6) UNIT VI2C Supply Voltage Range for I2C Interface 1.7 3.63 V fSCL SCL Clock Frequency 400 kHz VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V Vhys Hysteresis of Schmitt Trigger Input 0.05VDD V VOL Low-level Output Voltage (Open-drain) at 4mA Sink Current 0.4 V Ii Input Leakage for each SDA, SCL Pin -10 10 µA tSP Pulse Width of Spikes that must be Suppressed by the Input Filter 50 ns tAA SCL Falling Edge to SDA Output Data Valid 900 ns Ci Capacitance for each SDA and SCL Pin 10 pF tHD:STA Hold Time (Repeated) START Condition After this period, the first clock pulse is generated. 600 ns tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing 1300 ns tHIGH HIGH Period of the SCL Clock 600 ns tSU:STA Set-up Time for a Repeated START Condition 600 ns tHD:DAT Data Hold Time 30 ns tSU:DAT Data Set-up Time 100 ns tR Rise Time of both SDA and SCL Signals (Note 9) 20 + 0.1xCb ns tF Fall Time of both SDA and SCL Signals (Note 9) 20 + 0.1xCb ns tSU:STO Set-up Time for STOP Condition 600 ns tBUF Bus Free Time Between a STOP and START Condition 1300 ns Cb Capacitive Load for Each Bus Line 400 pF Rpull-up SDA and SCL System Bus Pull-up Resistor Maximum is determined by tR and tF 1kΩ Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 1MΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITION MIN (Note 6) TYP MAX (Note 6) UNIT |
Nº de peça semelhante - ISL29033IROZ-EVALZ |
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Descrição semelhante - ISL29033IROZ-EVALZ |
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