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LM2647 Folha de dados(PDF) 6 Page - Texas Instruments |
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LM2647 Folha de dados(HTML) 6 Page - Texas Instruments |
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6 / 42 page  LM2647 SNVS210F – JUNE 2003 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those with boldface apply over full Operating Junction Temperature range. VDD = V5 = 5V, VSGND = VPGND = 0V, VIN = 15V, VEN = 3V, RFADJ = 22.1K unless otherwise stated. (1) Symbol Parameter Conditions Min(2) Typical(3) Max(2) Units Reference VFB_REG FB Pin Voltage at Regualtion VDD = 4.5V to 5.5V, 591 600 609 mV (either FB Pin) VIN = 5.5V to 28V VFB Line Regulation VDD = 4.5V to 5.5V, 0.5 VIN = 5.5V to 28V IFB FB Pin Current (sourcing) VFB at regulation 20 100 nA Chip Supply IQ_VIN VIN Quiescent Current VFB1 = VFB2 = 0.7V 100 200 µA ISD_VN VIN Shutdown Current VEN = 0V 0 5 µA IQ_VDD VDD Quiescent Current VFB1 = VFB2 = 0.7V 2.5 4 mA ISD_VDD VDD Shutdown Current VEN = 0V 8 15 µA IQ_V5 V5 Normal Operating Current VFB1 = VFB2 = 0.7V 0.3 0.5 mA VFB1 = VFB2 = 0.5V 1 1.5 ISD_V5 V5 Shutdown Current VEN = 0V 0 5 µA IQ_BOOT BOOT Quiescent Current VFB1 = VFB2 = 0.7V 2 5 µA VFB1 = VFB2 = 0.5V 300 500 ISD_BOOT BOOT Shutdown Current VEN = 0V 1 5 µA VUVLO VDD UVLO Threshold VDD rising from 0V 3.9 4.2 4.5 V VDD UVLO Hysteresis VDD = V5 falling from VUVLO 0.5 0.7 0.9 V Logic IEN EN Input Current VEN = 0 to 5V 0 µA VEN_HI EN Input Logic High 2 1.8 V VEN_LO EN Input Logic Low 1.3 0.8 V FPWM Pull-down VFPWM = 2V 100 200 1000 k Ω VFPWM_HI FPWM Input Logic High 2 1.8 V VFPWM_LO FPWM Input Logic Low 1.3 0.8 V Power Good VPGOOD_HI Power Good Upper Threshold as FB voltage rising above VFB_REG 110 113 116 % a Percentage of Internal Reference VPGOOD_LOW Power Good Lower Threshold as FB voltage falling below VFB_REG 84 87 90 % a Percentage of Internal Reference Power Good Hysteresis 7 % ΔtPG_OK Power Good Delay From both output voltages “good” 10 20 30 µs to PGOOD assertion. ΔtPG_NOK From the first output voltage “bad” 4 7 10 to PGOOD de-assertion ΔtSD From Enable low to PGOOD low 0.03 0.1 PGOOD Saturation Voltage PGOOD de-asserted (Power Not 0.12 0.4 V Good) and sinking 1.5mA PGOOD Leakage Current PGOOD = 5V and asserted 0 1 µA OV and UV Protection Fault OVP Latch Threshold as a FB voltage rising above VFB_REG 125 130 135 % Percentage of Internal Reference (1) RFADJ is the frequency adjust resistor between FREQ pin and Ground. (2) All limits are specified at room temperature (standard face type) and at temperature extremes (bold face type). All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). (3) Typical numbers are at 25°C and represent the most likely norm. 6 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2647 |
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