LM2647

www.ti.com

SNVS210F – JUNE 2003 – REVISED APRIL 2013

PIN DESCRIPTION

(All pin numbers referred to here correspond to the TSSOP package)

Pin 1, SENSE1: Output voltage sense pin for Channel 1. It is tied directly to the output rail. The SENSE pin voltage is used together with

the VIN voltage (on Pin 22) to (internally) calculate the CCM (continuous conduction mode) duty cycle. This calculation is used by the IC to

set the minimum duty cycle in the SKIP mode to 85% of the CCM value. It is also used to set the adaptive duty cycle clamp (see Pin 3). An

internal 20

Ω resistor from the SENSE pin to ground discharges the output capacitor gently (Soft-shutdown) whenever Power Not Good is

signaled on Pin 9.

Pin 2, FB1: Feedback pin for Channel 1. This is the inverting input of the error amplifier. The voltage on this pin under regulation is

nominally at 0.6V. A Power Good window on this pin determines if the output voltage is within regulation limits (±13%). If the voltage (on

either channel) falls outside this window for more than 7µs, Power Not Good is signaled on the PGOOD pin (Pin 9). Output over-voltage

and under-voltage conditions are also detected by comparing the voltage on the Feedback pin with appropriate internal reference voltage

levels. If the voltage exceeds the safe window (±30%) for longer than 7µs, a fault condition is asserted. Then both the lower FETs are

latched ON and the upper FETs are latched OFF. When single channel operation is desired, the Feedback pins of both channels should be

connected together, near the IC. All other pins specific to the unused channel should be left floating (not connected to each other either).

Pin 3, COMP1: Compensation pin for Channel 1. This is also the output of the error amplifier of this channel. The voltage level on this pin is

compared with an internally generated ramp signal to set the duty cycle for normal regulation. Since the Feedback pin is the inverting input

of the same error amplifier, appropriate control loop compensation components are placed between this pin and the Feedback pin. The

COMP pin is internally pulled low during Soft-start so as to limit the duty cycle. Once Soft-start is completed, the voltage on this pin can

take up the value required to maintain output regulation. But an internal voltage clamp does not allow the pin to go much higher than the

steady-state requirement. This forms the adaptive duty cycle clamp feature which serves to limit the maximum allowable duty cycle and

peak currents under sudden overloads. But at the same time it has enough headroom to permit an adequate response to step loads within

the normal operating range.

Pin 4, SS1: Channel 1 Soft-start pin. A Soft-start capacitor is placed between this pin and ground. A typical capacitance of 0.1µF is always

recommended between this pin and ground. The IC connects an internal 1.8 k

between this pin and ground to discharge any remaining charge on the Soft-start capacitor under several conditions. These conditions

include the initial power-up sequence, start-up by toggling the EN pin, and also recovery from a fault condition. The purpose is to bring

down the voltage on both the Soft-start pins to below 100mV for obtaining reset. Reset having thus been obtained, an 11µA current source

at this pin charges up the Soft-start capacitor. The voltage on this pin controls the maximum duty cycle, and this produces a gradual ramp-

up of the output voltage, thereby preventing large inrush currents into the output capacitors. The voltage on this pin finally clamps close to

5V. This pin is again connected to the internal 115µA current sink whenever a current limit event is in progress. This sink current discharges

the Soft-start capacitor and forces the duty cycle low to protect the power components. When a fault condition is asserted (See Pin 2) the

SS pin is internally connected to ground via the 1.8 k

Ω resistor.

Pin 5, VDD: 5V supply rail for the control and logic sections of both channels. For normal operation to start, the voltage on this pin must be

brought above 4.5V. Subsequently, the voltage on this pin (including any ripple component) should not allowed to fall below 4V for a

duration longer than 7µs. Since this pin is also the supply rail for the internal control sections, it should be well-decoupled particularly at

high frequencies. A minimum 0.1µF-0.47µF (ceramic) capacitor should be placed on the component side very close to the IC with no

intervening vias between this capacitor and the VDD/SGND pins. If the voltage on Pin 5 falls below the lower UVLO threshold, both upper

FETs are latched OFF and lower FETs latched ON. Power Not Good is then also signaled immediately (on Pin 9). To effect recovery, the

EN pin must be taken below 0.8V and then back above 2V (with VDD held above 4.5V). Or the voltage on the VDD pin must be taken

below 1.0V and then back again above 4.5V (with EN pin held above 2V). Normal operation will then resume assuming that the fault

condition has cleared.

Pin 6, FREQ: Frequency adjust pin. The switching frequency (for both channels) is set by a resistor connected between this pin and

ground. A value of 22.1k

Ω sets the frequency to 300kHz (nominal). If the resistance is increased, the switching frequency falls. An

approximate relationship is that for every 7.3k

Ω increase (or decrease) in the value of the frequency adjust resistance, the time period (1/f)

increases (or decreases) by about 1µs.

Pin 7, SGND: Signal Ground pin. This is the lower rail for the control and logic sections of both channels. SGND should be connected on

the PCB to the system ground, which in turn is connected to PGND1 and PGND2. The layout is important and the recommendations in the

section LAYOUT GUIDELINES should be followed.

Pin 8, EN: IC Enable pin. When EN is taken high, both channels are enabled by means of a Soft-start power-up sequence (see Pin 4).

When EN is brought low, Power Not Good is signaled within 100ns. This causes Soft-shutdown to occur (see Pins 1 and 9). The Soft-start

capacitor is then discharged by an internal 1.8k

pin is toggled, a fault condition is not asserted. Therefore in this case, the lower FETs are not latched ON, even as the output voltage ramps

down, eventually falling below the under-voltage threshold. In fact, in this situation, both the upper and the lower FETs of the two channels

are latched OFF, until the Enable pin is taken high again. If a fault shutdown has occurred, taking the Enable pin low and then high again

(toggling), resets the internal latches, and the IC will resume normal switching operation.

Pin 9, PGOOD: Power Good output pin. An open-Drain logic output that is pulled high with an external pull-up resistor, indicating that both

output voltages are within a pre-defined Power Good window. Outside this window, the pin is internally pulled low (Power Not Good

signaled) provided the output error lasts for more than 7µs. But the pin is also pulled low within 100ns of the Enable pin being taken low,

irrespective of the output voltage level. Note that PGOOD must always be high before it can respond by going low. So regulation on both

channels must be achieved first. Further, for fault monitoring to be in place, PGOOD must have been high prior to occurrence of the fault

condition. Note that since under a fault assertion, the lower FETs are always latched ON, this will not happen if regulation has not been

already been achieved first. For correct signaling on this pin under single-channel operation, see description of Pin 2.

Copyright © 2003–2013, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: LM2647