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LM25088-Q1 Folha de dados(PDF) 11 Page - Texas Instruments

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Nome de Peças LM25088-Q1
Descrição Electrónicos  LM25088, LM25088-Q1 Wide Input Range Non-Synchronous Buck Controller
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LM25088-Q1 Folha de dados(HTML) 11 Page - Texas Instruments

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RRT =
152 pF
1
fSW
- 280 ns
LM25088, LM25088-Q1
www.ti.com
SNVS609J – DECEMBER 2008 – REVISED JANUARY 2015
8.3 Feature Description
8.3.1 High Voltage Low-Dropout Regulator
The LM25088 contains a high voltage, low-dropout regulator that provides the VCC bias supply for the controller
and the bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to an input voltage as high
as 42V. The output of the VCC regulator (7.8V) is internally current limited to 25 mA. Upon power up, the
regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds
the upper VCC UV threshold of 4.0V and the EN pin is greater than 1.2 Volts, the output (HG) is enabled and a
soft-start sequence begins. The output is terminated if VCC falls below its lower UV threshold (3.8V) or the EN
pin falls below 1.1V. When VIN is less than VCC regulation point of 7.8V, then the internal pass device acts as a
switch. Thereby, VCC tracks VIN with a voltage drop determined by the RDS(ON) of the internal switch and
operating current of the controller. The required VCC capacitor value is dependant on system startup
characteristics with a minimum value no less than 0.1 µF.
An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 8.2V, the internal regulator will be disabled. The VCC regulator series pass transistor
includes a diode between VCC and VIN that should not be forward biased in normal operation.
In high voltage applications, additional care should be taken to ensure that the VIN pin does not exceed the
absolute maximum voltage rating of 45V. During line or load transients, voltage ringing on the VIN pin that
exceeds the absolute maximum ratings may damage the IC. Both careful PC board layout and the use of high
quality bypass capacitors located close to the VIN and GND pins are essential.
8.3.2 Line Under-Voltage Detector
The LM25088 contains a dual level under-voltage lockout (UVLO) circuit. When the EN pin is below 0.4V, the
controller is in a low current shutdown mode. When the EN pin is greater than 0.4V but less than 1.2V, the
controller is in a standby mode. In standby mode the VCC regulator is active but the output switch is disabled
and the SS pin is held low. When the EN pin exceeds 1.2V and VCC exceeds the VCC UV threshold, the SS pin
and the output switch is enabled and normal operation begins. An internal 5 µA pull-up current source at the EN
pin configures the controller to be fully operational if the EN pin is left open.
An external VIN UVLO set-point voltage divider from VIN to GND can be used to set the minimum startup input
voltage of the controller. The divider must be designed such that the voltage at the EN pin exceeds 1.2V (typ)
when VIN is in the desired operating range. The internal 5 µA pull-up current source must be included in
calculations of the external set-point divider. 100 mV of hysteresis is included for both the shutdown and standby
thresholds. The EN pin is internally connected to a 1 k
Ω resistor and an 8V zener clamp. If the voltage at the EN
pin exceeds 8V, the bias current for the EN pin will increase at the rate of 1mA/V. The voltage at the EN pin
should never exceed 14V.
8.3.3 Oscillator and Sync Capability
The LM25088 oscillator frequency is set by a single external resistor connected between the RT pin and the
GND pin. The RT resistor should be located very close to the device. To set a desired oscillator frequency (fSW),
the necessary value of RT resistor can be calculated from the following equation:
(1)
The RT pin can also be used to synchronize the internal oscillator to an external clock. The internal oscillator is
synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The RT/SYNC pin
voltage must exceed 3V to trip the internal clock synchronization pulse detector. The free-running frequency
should be set nominally 15% below the external clock frequency and the pulse width applied to the RT/SYNC pin
must be less than 150ns. Synchronization to an external clock more than twice the free-running frequency can
produce abnormal behavior of the pulse-width modulator.
Copyright © 2008–2015, Texas Instruments Incorporated
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