Upper:

Lower:

V

=2.5V×

(driver)

R1+R2

R1

V

=2.3V×

(driver)

R1+R2

R1

.

I

OUT

D * D

2

TPIC74101-Q1

www.ti.com

SLIS140A – OCTOBER 2011 – REVISED DECEMBER 2014

7.3 Feature Description

7.3.1 Switch-Mode Input/Output Pins (L1, L2)

The external inductor for the switch-mode regulator is connected between pins L1 and L2. This inductor is placed

close to the pins to minimize parasitic effects. For stability, an inductor with 20

μH to 100 μH should be used.

noise. A low-ESR aluminum or tantalum input capacitor is recommended. The relevant parameters for the input

capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately 1.5 times the

maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck mode, the

RMS current is

, where D is the duty cycle and its maximum RMS current value is reached when

current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with the aluminum or

tantalum capacitors.

be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE, CLP, and

5Vg_ENABLE).

input voltage without effecting the device operation. The resistor divider network is programmed to set the

undervoltage detection threshold on this pin (see the application schematic). The input has a typical hysteresis of

(1)

7.3.6 Reset Delay Timer Pin (REST)

The REST pin sets the desired delay time to assert the RESET pin low after the 5-V supply has exceeded 4.65 V

(typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in the range of 2.2 nF

to 150 nF. The delay time is calculated using the following equation:

7.3.7 Reset Pin (RESET)

The RESET pin is an open-drain output. The power-on reset output is asserted low until the output voltage

exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE pin is

low, RESET is immediately asserted low regardless of the output voltage.

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