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LM34927 Folha de dados(PDF) 3 Page - Texas Instruments

Nome de Peças LM34927
Descrição Electrónicos  LM34927 Integrated Secondary-Side Bias Regulator for Isolated DC-DC Converters
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

LM34927 Folha de dados(HTML) 3 Page - Texas Instruments

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SW
BST
VCC
FB
8
7
6
5
1
2
3
4
UVLO
RON
RTN
VIN
WSON-8
Exp Pad
UVLO
3
RON
4
RTN
1
VIN
2
8
SW
7
BST
6
VCC
5
FB
SO
PowePAD-8
Exp Pad
LM34927
www.ti.com
SNVS799G – APRIL 2012 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
8-Pin SO PowerPAD
DDA Package
Top View
Connect Exposed Pad to RTN
8-Pin WSON With Exposed Thermal Pad
NGU Package
Top View
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
NAME
1
RTN
Ground
Ground connection of the integrated circuit.
2
VIN
I
Input Voltage
Operating input range is 7.5 V to 100 V.
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
Input Pin of Undervoltage
3
UVLO
I
enabled when UVLO is above 1.225 V to provide hysteresis.
Comparator
When UVLO pin is pulled below 0.66 V externally, the parts goes
in shutdown mode.
A resistor between this pin and VIN sets the switch on-time as a
4
RON
I
On-Time Control
function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
This pin is connected to the inverting input of the internal
5
FB
I
Feedback
regulation comparator. The regulation level is 1.225 V.
Output from the Internal High
The internal VCC regulator provides bias supply for the gate
Voltage Series Pass Regulator.
drivers and other internal circuitry. A 1.0-
μF decoupling capacitor
6
VCC
O
Regulated at
is recommended.
7.6 V.
An external capacitor is required between the BST and SW pins
7
BST
I
Bootstrap Capacitor
(0.01-
μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
Power switching node. Connect to the output inductor and
8
SW
O
Switching Node
bootstrap capacitor.
Exposed pad must be connected to RTN pin. Connect to system
EP
Exposed Pad
ground plane on application board for reduced thermal resistance.
Copyright © 2012–2014, Texas Instruments Incorporated
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