UC2875EP

PHASE SHIFT RESONANT CONTROLLER

SGLS233A − FEBRUARY 2004 − REVISED DECEMBER 2008

1

POST OFFICE BOX 655303

− One Assembly/Test Site, One Fabrication

Site

−25

°C to 110°C

Sources (DMS) Support

Topologies

Frequencies to 1 MHz

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

Cycle Restart

description/ordering information

The UC2875 integrated circuit implements control of a bridge power stage by phase-shifting the switching of

one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination

with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be

configured to provide control in either voltage or current mode operation, with a separate over-current shutdown

for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay,

providing time to allow the resonant switching action, is independently controllable for each output pair (A−B,

C−D).

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−25

°C to 110°C

SOP − DW

Tape and reel

UC2875SDWREP

UC2875SEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright

 2004 − 2008 Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DW PACKAGE

(TOP VIEW)

NC = No Connect

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28

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15

VREF

E/AOUT

EA−

EA+

CS+

SOFTSTART

GND

GND

GND

DELAYSET C−D

NC

OUTD

OUTC

VC

GND

RAMP

SLOPE

CLOCKSYNC

FREQSET

DELAYSET A−B

GND

GND

GND

NC

OUTA

OUTB

PWRGND

VIN