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LC87F1K64AUWA-2H Folha de dados(PDF) 4 Page - ON Semiconductor

Nome de Peças LC87F1K64AUWA-2H
Descrição Electrónicos  8-bit Microcontroller
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
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LC87F1K64A
No.A2197-4/35
Interrupts
• 44 sources, 10 vectors
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of
the level equal to or lower than the current interrupt level is not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the lowest vector
address is given priority.
No.
Vector
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/UHC-A bus active/UHC-B bus active/remote control receive
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6/UHC-A device connected, disconnected, resumed
6
0002BH
H or L
T1L/T1H/INT7/AIF start/SMIIC0/UHC-B device connected, disconnected, resumed
7
00033H
H or L
SIO0/UART1 reception completed
8
0003BH
H or L
SIO1/SIO4/UART1 buffer empty/UART1 transmission completed/AIF end
9
00043H
H or L
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5/UHC-SOF
• Priority levels X > H > L
• When interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given
priority.
Subroutine Stack Levels: Up to 4096 levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillator Circuit and PLL
• Medium-speed RC oscillator circuit (internal): For system clock (approx. 1MHz)
• Low-speed RC oscillator circuit (internal):
For system clock, timer, and watchdog timer (approx. 30kHz)
• CF oscillator circuit:
For system clock
• Crystal oscillator circuit:
For system clock and time-of-day clock
• PLL circuit (internal):
For USB interface (see Fig. 5) and audio interface (see Fig. 6)
Internal Reset Functions
• Power-on reset (POR) function
1) POR is activated at power-on.
2) POR release voltage can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V)
by setting options.
• Low voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a threshold level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, and 4.28V) can be selected by setting options.


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